Mixed analog/digital hardware synthesis of artificial neural networks. - Arun Achyuthan; Mohamed I. Elmasry (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Leakage Reduction techniques in a 0.13um SRAM Cell. - Sergey Romanovsky; Arun Achyuthan; Sreedhar Natarajan; Wing Leung (VLSI Design, 2004)

A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS. - Sergey Romanovsky; Atul Katoch; Arun Achyuthan; C. O'Connell; Sreedhar Natarajan; C. Huang; Chuan-Yu Wu; Min-Jer Wang; C. J. Wang; P. Chen; R. Hsieh (ISSCC, 2008)

12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications. - Michael Clinton; Hank Cheng; Hung-Jen Liao; Robin Lee; Ching-Wei Wu; Johnny Yang; Hau-Tai Hsieh; Frank Wu; Jung-Ping Yang; Atul Katoch; Arun Achyuthan; Donald Mikan; et al. (ISSCC, 2017)