Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor. - Raghuram S. Tupuri; Arun Krishnamachary; Jacob A. Abraham (DAC, 1999)

Timing Verification and Delay Test Generation for Hierarchical Designs. - Arun Krishnamachary; Jacob A. Abraham; Raghuram S. Tupuri (VLSI Design, 2001)

A Comprehensive Fault Model for Deep Submicron Digital Circuits. - Jacob A. Abraham; Arun Krishnamachary; Raghuram S. Tupuri (DELTA, 2002)

Test generation for resistive opens in CMOS. - Arun Krishnamachary; Jacob A. Abraham (ACM Great Lakes Symposium on VLSI, 2002)

Effects of Multi-cycle Sensitization on Delay Tests. - Arun Krishnamachary; Jacob A. Abraham (VLSI Design, 2003)

Case Study on Speed Failure Causes in a Microprocessor. - Kip Killpack; Suriyaprakash Natarajan; Arun Krishnamachary; Pouria Bastani (IEEE Des. Test Comput., 2008)

Path coverage based functional test generation for processor marginality validation. - Suriyaprakash Natarajan; Arun Krishnamachary; Eli Chiprout; Rajesh Galivanche (ITC, 2010)