Efficient Finite State Machine Encoding for Defending Against Laser Fault Injection Attacks. - Aruna Jayasena; Khushboo Rani; Prabhat Mishra 001 (ICCD, 2022)

Network-on-Chip Trust Validation Using Security Assertions. - Aruna Jayasena; Binod Kumar; Subodha Charles; Hasini Witharana; Prabhat Mishra 001 (J. Hardw. Syst. Secur., 2022)

DETER: Design for Trust utilizing Rareness Reduction. - Aruna Jayasena; Prabhat Mishra 001 (CoRR, 2023)

Sequence-Based Incremental Concolic Testing of RTL Models. - Hasini Witharana; Aruna Jayasena; Prabhat Mishra 001 (CoRR, 2023)

Logic Locking based Trojans: A Friend Turns Foe. - Yuntao Liu 001; Aruna Jayasena; Prabhat Mishra 001; Ankur Srivastava 001 (CoRR, 2023)

Automated Generation of Security Assertions for RTL Models. - Hasini Witharana; Aruna Jayasena; Andrew Whigham; Prabhat Mishra 001 (ACM J. Emerg. Technol. Comput. Syst., 2023)

TVLA*: Test Vector Leakage Assessment on Hardware Implementations of Asymmetric Cryptography Algorithms. - Aruna Jayasena; Emma Andrews; Prabhat Mishra 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Scalable Detection of Hardware Trojans Using ATPG-Based Activation of Rare Events. - Aruna Jayasena; Prabhat Mishra 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

EvilCS: An Evaluation of Information Leakage through Context Switching on Security Enclaves. - Aruna Jayasena; Richard Bachmann; Prabhat Mishra 001 (DATE, 2024)

Design for Trust Utilizing Rareness Reduction. - Aruna Jayasena; Prabhat Mishra 001 (VLSID, 2024)

Directed Test Generation for Hardware Validation: A Survey. - Aruna Jayasena; Prabhat Mishra 001 (ACM Comput. Surv., 2024)

Incremental Concolic Testing of Register-Transfer Level Designs. - Hasini Witharana; Aruna Jayasena; Prabhat Mishra 001 (ACM Trans. Design Autom. Electr. Syst., 2024)

HIVE: Scalable Hardware-Firmware Co-Verification Using Scenario-Based Decomposition and Automated Hint Extraction. - Aruna Jayasena; Prabhat Mishra 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Formal verification of bioinformatics software using model checking and theorem proving. - Hansika Weerasena; Aruna Jayasena; Christina Boucher 001; Prabhat Mishra 001 (Briefings Bioinform., 2025)

CiseLeaks: Information Leakage Assessment of Cryptographic Instruction Set Extension Prototypes. - Aruna Jayasena; Richard Bachmann; Prabhat Mishra 001 (IEEE Trans. Inf. Forensics Secur., 2025)

FirmWall: Directed Symbolic Execution of Firmware Binaries for Defending Against Unauthorized System Calls. - Aruna Jayasena; Prabhat Mishra 001 (IEEE Trans. Inf. Forensics Secur., 2025)

Information Leakage Through Physical Layer Supply Voltage Coupling Vulnerability. - Sahan Sanjaya; Aruna Jayasena; Prabhat Mishra 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

SleepWalk: Exploiting Context Switching and Residual Power for Physical Side-Channel Attacks. - Sahan Sanjaya; Aruna Jayasena; Prabhat Mishra 001 (CoRR, 2025)