Economic return to the previous state for any nearest neighbourhood reversible autonomous finite state machines. - Pabitra Pal Choudhury; Arup Roy Chowdhury (Inf. Sci., 2000)

Generic and programmable Timing Generator for CCD detectors. - Parth Shah; Bhavesh Soni; Mohammad Waris; Rajiv Kumaran; Sanjeev Mehta; Arup Roy Chowdhury (ICACCI, 2014)

Implementation of high performance Readout Integrated Circuit. - Hari Shanker Gupta; Subhananda Chakrabarti; Maryam Shojaei Baghini; Dinesh Kumar Sharma; A. S. Kiran Kumar; Sanjeev Mehta; Sandip Paul; Ravi Shankar Chaurasia; Arup Roy Chowdhury (MWSCAS, 2014)

An all digital delay lock loop architecture for high precision timing generator. - Mohammad Waris; Urvi Mehta; Rajiv Kumaran; Sanjeev Mehta; Arup Roy Chowdhury (VDAT, 2015)

Large Dynamic Range Readout Integrated Circuit for Infrared Detectors. - Hari Shanker Gupta; Sanjeev Mehta; Maryam Shojaei Baghini; Arup Roy Chowdhury; A. S. Kiran Kumar; Dinesh Kumar Sharma (VLSID, 2019)

A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC. - Satyajit Mohapatra; Hari Shanker Gupta; Nihar Ranjan Mohapatra; Sanjeev Mehta; Arup Roy Chowdhury; Nisha Pandya (VLSID, 2019)