On Reference String Generation Processes. - Arvind 001; Richard Y. Kain; Eitan Sadeh (SOSP, 1973)

A Computer Capable of Exchanging Processors for Time. - Arvind 001; Kim P. Gostelow (IFIP Congress, 1977)

Some Relationships Between Asynchronous Interpreters of a Dataflow Language. - Arvind 001; Kim P. Gostelow (Formal Description of Programming Concepts, 1977)

Indeterminancy, Monitors, and Dataflow. - Arvind 001; Kim P. Gostelow; Wil Plouffe (SOSP, 1977)

Streams and Managers. - Arvind 001; J. Dean Brock (Operating Systems Engineering, 1980)

Data Flow Languages and Architecture. - Arvind 001 (ISCA, 1981)

Data Flow Systems - Guest Editors' Introduction. - Tilak Agerwala; Arvind 001 (Computer, 1982)

The U-Interpreter. - Arvind 001; Kim P. Gostelow (Computer, 1982)

A Critique of Multiprocessing von Neumann Style - Arvind 001; Robert A. Iannucci (ISCA, 1983)

Resource managers in functional programming. - Arvind 001; J. Dean Brock (J. Parallel Distributed Comput., 1984)

Demand-Driven Evaluation on Dataflow Machine. - Arvind 001 (FSTTCS, 1985)

Efficient Demand-Driven Evaluation - Part 1. - Keshav Pingali; Arvind 001 (ACM Trans. Program. Lang. Syst., 1985)

Efficient Demand-Driven Evaluation - Part 2. - Keshav Pingali; Arvind 001 (ACM Trans. Program. Lang. Syst., 1986)

Two Fundamental Issues in Multiprocessing. - Arvind 001; Robert A. Iannucci (Parallel Computing in Science and Engineering, 1987)

Resource Requirements of Dataflow Programs. - David E. Culler; Arvind 001 (ISCA, 1988)

Future Scientific Programming on Parallel Machines. - Arvind 001; Kattamuri Ekanadham (J. Parallel Distributed Comput., 1988)

P-TAC: A Parallel Intermediate Language. - Zena M. Ariola; Arvind 001 (FPCA, 1989)

I-Structures: Data Structures for Parallel Computing. - Arvind 001; Rishiyur S. Nikhil; Keshav Pingali (ACM Trans. Program. Lang. Syst., 1989)

Executing a Program on the MIT Tagged-Token Dataflow Architecture. - Arvind 001; Rishiyur S. Nikhil (IEEE Trans. Computers, 1990)

Compilation of Id. - Zena M. Ariola; Arvind 001 (LCPC, 1991)

A Syntactic Approach to Program Transformations. - Zena M. Ariola; Arvind 001 (PEPM, 1991)

*T: A Multithreaded Massively Parallel Architecture. - Rishiyur S. Nikhil; Gregory M. Papadopoulos; Arvind 001 (ISCA, 1992)

The Evolution of Dataflow Architectures: from Static Dataflow to P-RISC. - Arvind 001; Stephen Brobst (Int. J. High Speed Comput., 1993)

Performance Studies of Id on the Monsoon Dataflow System. - James E. Hicks; Derek Chiou; Boon Seong Ang; Arvind 001 (J. Parallel Distributed Comput., 1993)

START-NG: Delivering Seamless Parallel Computing. - Derek Chiou; Boon Seong Ang; Robert Greiner; Arvind 001; James C. Hoe; Michael J. Beckerle; James E. Hicks; G. Andrew Boughton (Euro-Par, 1995)

Semantics of Barriers in a Non-Strict, Implicitly-Parallel Language. - Shail Aditya; Arvind 001; Joseph E. Stoy (FPCA, 1995)

Properties of a First-Order Functional Language with Sharing. - Zena M. Ariola; Arvind 001 (Theor. Comput. Sci., 1995)

Performance tuning scientific codes for dataflow execution. - Andrew Shaw; Arvind 001; R. Paul Johnson (IEEE PACT, 1996)

A Lambda Calculus with Letrecs and Barriers. - Arvind 001; Jan-Willem Maessen; Rishiyur S. Nikhil; Joseph E. Stoy (FSTTCS, 1996)

A Multithreaded Substrate and Compilation Model for the Implicity Parallel Language pH. - Arvind 001; Alejandro Caro; Jan-Willem Maessen; Shail Aditya (LCPC, 1996)

The StarT-Voyager Parallel System. - Boon Seong Ang; Derek Chiou; Larry Rudolph; Arvind 001 (IEEE PACT, 1998)

Message passing support on StarT-Voyager. - Boon Seong Ang; Derek Chiou; Larry Rudolph; Arvind 001 (HiPC, 1998)

StarT-Voyager: A Flexible Platform for Exploring Scalable SMP Issues. - Boon Seong Ang; Derek Chiou; Daniel L. Rosenband; Mike Ehrlich; Larry Rudolph; Arvind 001 (SC, 1998)

LambdaS: an implicitly parallel lambda-calculus with letrec, synchronization and side-effects. - Arvind 001; Jan-Willem Maessen; Rishiyur S. Nikhil; Joseph E. Stoy (HLCL, 1998)

A Comparison of Implicitly Parallel Multithreaded and Data-Parallel Implementations of an Ocean Model. - Andrew Shaw; Arvind 001; Kyoo-Chan Cho; Christopher Hill; R. Paul Johnson; John Marshall (J. Parallel Distributed Comput., 1998)

CACHET: an adaptive cache coherence protocol for distributed shared-memory systems. - Xiaowei Shen; Arvind 001; Larry Rudolph (International Conference on Supercomputing, 1999)

Hardware Synthesis from Term Rewriting Systems. - James C. Hoe; Arvind 001 (VLSI, 1999)

Commit-Reconcile & Fences (CRF): A New Memory Model for Architects and Compiler Writers. - Xiaowei Shen; Arvind 001; Larry Rudolph (ISCA, 1999)

Using term rewriting systems to design and verify processors. - Arvind 001; Xiaowei Shen (IEEE Micro, 1999)

Synthesis of Operation-Centric Hardware Descriptions. - James C. Hoe; Arvind 001 (ICCAD, 2000)

Micro-Architectures of High Performance, Multi-User System Area Network Interface Cards. - Boon Seong Ang; Derek Chiou; Larry Rudolph; Arvind 001 (IPDPS, 2000)

Improving the Java memory model using CRF. - Jan-Willem Maessen; Arvind 001; Xiaowei Shen (OOPSLA, 2000)

From Monsoon to StarT-Voyager: University-Industry Collaboration. - Arvind 001; Anton T. Dahbura; Alejandro Caro (IEEE Micro, 2000)

Implicit parallel programming in pH. - Rishiyur S. Nikhil; Arvind 001 (Morgan Kaufmann, 2001)

Proofs of Correctness of Cache-Coherence Protocols. - Joseph E. Stoy; Xiaowei Shen; Arvind 001 (FME, 2001)

Bluespec: A language for hardware design, simulation, synthesis and verification Invited Talk. - Arvind 001 (MEMOCODE, 2003)

Modular scheduling of guarded atomic actions. - Daniel L. Rosenband; Arvind 001 (DAC, 2004)

Rethinking Computer Architecture Research. - Arvind 001 (HiPC, 2004)

High-level synthesis: an essential ingredient for designing complex ASICs. - Arvind 001; Rishiyur S. Nikhil; Daniel L. Rosenband; Nirav Dave (ICCAD, 2004)

Rate Guarantees and Overload Protection in Input-Queued Switches. - Hari Balakrishnan; Srinivas Devadas; Douglas Ehlert; Arvind 001 (INFOCOM, 2004)

Operation-centric hardware description and synthesis. - James C. Hoe; Arvind 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Building up to macroprogramming: an intermediate language for sensor networks. - Ryan Newton; Arvind 001; Matt Welsh (IPSN, 2005)

Automatic synthesis of cache-coherence protocol processors using Bluespec. - Nirav Dave; Man Cheuk Ng; Arvind 001 (MEMOCODE, 2005)

Research accelerator for multiple processors. - David A. Patterson 001; Arvind 001; Krste Asanovic; Derek Chiou; James C. Hoe; Christos Kozyrakis; Shih-Lien Lu; Mark Oskin; Jan M. Rabaey; John Wawrzynek (Hot Chips Symposium, 2006)

Memory Model = Instruction Reordering + Store Atomicity. - Arvind 001; Jan-Willem Maessen (ISCA, 2006)

802.11a transmitter: a case study in microarchitectural exploration. - Nirav Dave; Michael Pellauer; S. Gerding; Arvind 001 (MEMOCODE, 2006)

UNUM: A Tinker-Toy Approach to Building Multicore PowerPC Microarchitectures. - Arvind 001 (VLSI Design, 2006)

Store Atomicity for Transactional Memory. - Jan-Willem Maessen; Arvind 001 (TV@FLoC, 2006)

A Mobile Phone Ecosystem: MIT and Nokia's Joint Research Venture. - Arvind 001; Jamey Hicks (IEEE Intell. Syst., 2006)

Scheduling as Rule Composition. - Nirav Dave; Arvind 001; Michael Pellauer (MEMOCODE, 2007)

From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols. - Man Cheuk Ng; Muralidaran Vijayaraghavan; Nirav Dave; Arvind 001; Gopal Raghavan; Jamey Hicks (MEMOCODE, 2007)

Getting Formal Verification into Design Flow. - Arvind 001; Nirav Dave; Michael Katelman (FM, 2008)

A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. - Michael Pellauer; Muralidaran Vijayaraghavan; Michael Adler; Arvind 001; Joel S. Emer (FPGA, 2008)

Synthesis from multi-cycle atomic actions as a solution to the timing closure problem. - Michal Karczmarek; Arvind 001 (ICCAD, 2008)

Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. - Michael Pellauer; Muralidaran Vijayaraghavan; Michael Adler; Arvind 001; Joel S. Emer (ISPASS, 2008)

Hands-on Introduction to Bluespec System Verilog (BSV) (Abstract). - Arvind 001; Rishiyur S. Nikhil (MEMOCODE, 2008)

H.264 Decoder: A Case Study in Multiple Design Points. - Kermin Fleming; Chun-Chieh Lin; Nirav Dave; Arvind 001; Gopal Raghavan; Jamey Hicks (MEMOCODE, 2008)

Advances in ESL Design. - Rajesh Gupta 001; Arvind 001; Gérard Berry; Forrest Brewer (IEEE Des. Test Comput., 2008)

Bounded Dataflow Networks and Latency-Insensitive circuits. - Muralidaran Vijayaraghavan; Arvind 001 (MEMOCODE, 2009)

A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs. - Michael Pellauer; Muralidaran Vijayaraghavan; Michael Adler; Arvind 001; Joel S. Emer (ACM Trans. Reconfigurable Technol. Syst., 2009)

Airblue: a system for cross-layer wireless protocol development. - Man Cheuk Ng; Kermin Elliott Fleming; Mythili Vutukuru; Samuel Gross; Arvind 001; Hari Balakrishnan (ANCS, 2010)

Is hardware innovation over? - Arvind 001 (HPCA, 2010)

A design flow based on modular refinement. - Nirav Dave; Man Cheuk Ng; Michael Pellauer; Arvind 001 (MEMOCODE, 2010)

A Comparative Evaluation of High-Level Hardware Synthesis Using Reed-Solomon Decoder. - Abhinav Agarwal; Man Cheuk Ng; Arvind 001 (IEEE Embed. Syst. Lett., 2010)

Programming Multicores: Do Applications Programmers Need to Write Explicitly Parallel Programs? - Arvind 001; David I. August; Keshav Pingali; Derek Chiou; Resit Sendag; Joshua J. Yi (IEEE Micro, 2010)

Automatic generation of hardware/software interfaces. - Arvind 001 (CASES, 2011)

WiLIS: Architectural modeling of wireless systems. - Kermin Elliott Fleming; Man Cheuk Ng; Samuel Gross; Arvind 001 (ISPASS, 2011)

Verification of microarchitectural refinements in rule-based systems. - Nirav Dave; Michael Katelman; Myron King; Arvind 001; José Meseguer 001 (MEMOCODE, 2011)

Improving performance and lifetime of solid-state drives using hardware-accelerated compression. - Sungjin Lee 001; Jihoon Park; Kermin Fleming; Arvind 001; Jihong Kim 001 (IEEE Trans. Consumer Electron., 2011)

Automatic generation of hardware/software interfaces. - Myron King; Nirav Dave; Arvind 001 (ASPLOS, 2012)

Leveraging latency-insensitivity to ease multiple FPGA design. - Kermin Elliott Fleming; Michael Adler; Michael Pellauer; Angshuman Parashar; Arvind 001; Joel S. Emer (FPGA, 2012)

Fast and cycle-accurate modeling of a multicore processor. - Asif Khan 005; Muralidaran Vijayaraghavan; Silas Boyd-Wickizer; Arvind 001 (ISPASS, 2012)

A general technique for deterministic model-cycle-level debugging. - Asif Khan 005; Muralidaran Vijayaraghavan; Arvind 001 (MEMOCODE, 2012)

Generating infrastructure for FPGA-accelerated applications. - Myron King; Asif Khan 005; Abhinav Agarwal; Oriol Arcas; Arvind 001 (FPL, 2013)

Leveraging rule-based designs for automatic power domain partitioning. - Abhinav Agarwal; Arvind 001 (ICCAD, 2013)

Bluespec and Haskell. - Arvind 001 (FPCDSL@ICFP, 2013)

Modular compilation of guarded atomic actions. - Muralidaran Vijayaraghavan; Nirav Dave; Arvind 001 (MEMOCODE, 2013)

Scalable multi-access flash store for big data analytics. - Sang Woo Jun; Ming Liu; Kermin Elliott Fleming; Arvind 001 (FPGA, 2014)

High-throughput implementation of a million-point sparse Fourier Transform. - Abhinav Agarwal; Haitham Hassanieh; Omid Abari; Ezzeldin Hamed; Dina Katabi; Arvind 001 (FPL, 2014)

A new synthesis procedure for atomic rules containing multi-cycle function blocks. - Michal Karczmarek; Arvind 001; Muralidaran Vijayaraghavan (MEMOCODE, 2014)

BlueDBM: A multi-access, distributed flash store for Big Data analytics. - Arvind 001 (ASAP, 2015)

Modular Deductive Verification of Multiprocessor Hardware Designs. - Muralidaran Vijayaraghavan; Adam Chlipala; Arvind 001; Nirav Dave (CAV (2), 2015)

A transport-layer network for distributed FPGA platforms. - Sang Woo Jun; Ming Liu; Shuotao Xu; Arvind 001 (FPL, 2015)

BlueDBM: an appliance for big data analytics. - Sang Woo Jun; Ming Liu; Sungjin Lee 001; Jamey Hicks; John Ankcorn; Myron King; Shuotao Xu; Arvind 001 (ISCA, 2015)

Large-scale high-dimensional nearest neighbor search using flash memory with in-store processing. - Sang Woo Jun; Chanwoo Chung; Arvind 001 (ReConFig, 2015)

Constructive computer architecture. - Arvind 001 (WCAE, 2015)

Refactored Design of I/O Architecture for Flash Storage. - Sungjin Lee 001; Jihong Kim 001; Arvind 001 (IEEE Comput. Archit. Lett., 2015)

Big Data Analytics on Flash Storage with Accelerators. - Arvind 001 (PACT, 2016)

minFlash: A minimalistic clustered flash array. - Ming Liu; Sang Woo Jun; Sungjin Lee 001; Jamey Hicks; Arvind 001 (DATE, 2016)

Application-Managed Flash. - Sungjin Lee 001; Ming Liu; Sang Woo Jun; Shuotao Xu; Jihong Kim 001; Arvind 001 (FAST, 2016)

In-storage embedded accelerator for sparse pattern processing. - Sang Woo Jun; Huy T. Nguyen; Vijay Gadepally; Arvind 001 (HPEC, 2016)

Taming Weak Memory Models. - Sizhuo Zhang; Arvind 001; Muralidaran Vijayaraghavan (CoRR, 2016)

Validating Simplified Processor Models in Architectural Studies. - Sizhuo Zhang; Andrew Wright; Daniel Sánchez 003; Arvind 001 (CoRR, 2016)

BlueCache: A Scalable Distributed Flash-based Key-value Store. - Shuotao Xu; Sungjin Lee 001; Sang Woo Jun; Ming Liu; Jamey Hicks; Arvind 001 (Proc. VLDB Endow., 2016)

BlueDBM: Distributed Flash Storage for Big Data Analytics. - Sang Woo Jun; Ming Liu; Sungjin Lee 001; Jamey Hicks; John Ankcorn; Myron King; Shuotao Xu; Arvind 001 (ACM Trans. Comput. Syst., 2016)

Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility. - Sizhuo Zhang; Muralidaran Vijayaraghavan; Arvind 001 (PACT, 2017)

Terabyte Sort on FPGA-Accelerated Flash Storage. - Sang Woo Jun; Shuotao Xu; Arvind 001 (FCCM, 2017)

Lightweight KV-based Distributed Store for Datacenters. - Chanwoo Chung; Jinhyung Koo; Arvind 001; Sungjin Lee 001 (HotStorage, 2017)

An Operational Framework for Specifying Memory Models using Instantaneous Instruction Execution. - Sizhuo Zhang; Muralidaran Vijayaraghavan; Arvind 001 (CoRR, 2017)

Weak Memory Models with Matching Axiomatic and Operational Definitions. - Sizhuo Zhang; Muralidaran Vijayaraghavan; Dan Lustig; Arvind 001 (CoRR, 2017)

BigSparse: High-performance external graph analytics. - Sang Woo Jun; Andy Wright; Sizhuo Zhang; Shuotao Xu; Arvind 001 (CoRR, 2017)

Kami: a platform for high-level parametric hardware specification and its modular verification. - Joonwon Choi; Muralidaran Vijayaraghavan; Benjamin Sherman; Adam Chlipala; Arvind 001 (Proc. ACM Program. Lang., 2017)

Low-power appliances for big-data analytics using flash storage and hardware accelerators. - Arvind 001 (CF, 2018)

GraFBoost: Using Accelerated Flash Storage for External Graph Analytics. - Sang Woo Jun; Andy Wright; Sizhuo Zhang; Shuotao Xu; Arvind 001 (ISCA, 2018)

Constructing a Weak Memory Model. - Sizhuo Zhang; Muralidaran Vijayaraghavan; Andrew Wright; Mehdi Alipour; Arvind 001 (ISCA, 2018)

An energy-efficient reconfigurable DTLS cryptographic engine for End-to-End security in iot applications. - Utsav Banerjee; Chiraag Juvekar; Andrew Wright; Arvind 001; Anantha P. Chandrakasan (ISSCC, 2018)

Composable Building Blocks to Open up Processor Design. - Sizhuo Zhang; Andrew Wright; Thomas Bourgeat; Arvind 001 (MICRO, 2018)

LightStore: Software-defined Network-attached Key-value Drives. - Chanwoo Chung; Jinhyung Koo; Junsu Im; Arvind 001; Sungjin Lee 001 (ASPLOS, 2019)

MI6: Secure Enclaves in a Speculative Out-of-Order Processor. - Thomas Bourgeat; Ilia A. Lebedev; Andrew Wright; Sizhuo Zhang; Arvind 001; Srinivas Devadas (MICRO, 2019)

An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications. - Utsav Banerjee; Andrew Wright; Chiraag Juvekar; Madeleine Waller; Arvind 001; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2019)

Proteus: Language and Runtime Support for Self-Adaptive Software Development. - Saeid Barati 001; Ferenc A. Bartha; Swarnendu Biswas; Robert Cartwright; Adam Duracz; Donald S. Fussell; Henry Hoffmann; Connor Imes; Jason E. Miller; Nikita Mishra; Arvind 001; Dung Nguyen; et al. (IEEE Softw., 2019)

AQUOMAN: An Analytic-Query Offloading Machine. - Shuotao Xu; Thomas Bourgeat; Tianhao Huang; Hojun Kim; Sungjin Lee 001; Arvind 001 (MICRO, 2020)

The essence of Bluespec: a core language for rule-based hardware design. - Thomas Bourgeat; Clément Pit-Claudel; Adam Chlipala; Arvind 001 (PLDI, 2020)

PinK: High-speed In-storage Key-value Store with Bounded Tails. - Junsu Im; Jinwook Bae; Chanwoo Chung; Arvind 001; Sungjin Lee 001 (USENIX ATC, 2020)

Effective simulation and debugging for a high-level hardware language using software compilers. - Clément Pit-Claudel; Thomas Bourgeat; Stella Lau; Arvind 001; Adam Chlipala (ASPLOS, 2021)

FlexMiner: A Pattern-Aware Accelerator for Graph Pattern Mining. - Xuhao Chen 001; Tianhao Huang; Shuotao Xu; Thomas Bourgeat; Chanwoo Chung; Arvind 001 (ISCA, 2021)

A Case for Application-Managed Flash. - Jinhyung Koo; Chanwoo Chung; Arvind 001; Sungjin Lee 001 (IEEE Trans. Computers, 2021)

Design of LSM-tree-based Key-value SSDs with Bounded Tails. - Junsu Im; Jinwook Bae; Chanwoo Chung; Arvind 001; Sungjin Lee 001 (ACM Trans. Storage, 2021)

Hemiola: A DSL and Verification Tools to Guide Design and Proof of Hierarchical Cache-Coherence Protocols. - Joonwon Choi; Adam Chlipala; Arvind 001 (CAV (2), 2022)

Efficient and Scalable Graph Pattern Mining on GPUs. - Xuhao Chen 001; Arvind 001 (OSDI, 2022)

Identifying Money Laundering Subgraphs on the Blockchain. - Kiwhan Song; Mohamed Ali Dhraief; Muhua Xu; Locke Cai; Xuhao Chen 001; Arvind Mithal; Jie Chen 007 (ICAIF, 2024)

The Shape of Money Laundering: Subgraph Representation Learning on the Blockchain with the Elliptic2 Dataset. - Claudio Bellei; Muhua Xu; Ross Phillips; Tom Robinson; Mark Weber; Tim Kaler; Charles E. Leiserson; Arvind 001; Jie Chen 007 (CoRR, 2024)

Making Concurrent Hardware Verification Sequential. - Thomas Bourgeat; Jiazheng Liu; Adam Chlipala; Arvind 001 (PLDI, 2025)

Leveraging ASIC AI Chips for Homomorphic Encryption. - Jianming Tong; Tianhao Huang; Leo de Castro; Anirudh Itagi; Jingtian Dang; Anupam Golder; Asra Ali; Jevin Jiang; Arvind 001; G. Edward Suh; Tushar Krishna (CoRR, 2025)