A 2.8-W Q-Band High-Efficiency Power Amplifier. - Michael V. Aust; Arvind K. Sharma; Owen Fordham; Ronald Grundbacher; Richard To; Roger S. Tsai; Richard Lai 002 (IEEE J. Solid State Circuits, 2006)

Saksham: Customizable x86 Based Multi-Core Microprocessor Simulator. - Amol Vasudeva; Arvind Kumar Sharma; Ashish Kumar (CICSyN, 2009)

An empirical delta delay model for highly scaled CMOS inverter considering Well Proximity Effect. - Bijay Kumar Dalai; N. Karnnan; Arvind Kumar Sharma; Bulusu Anand (VDAT, 2014)

Efficient static D-latch standard cell characterization using a novel setup time model. - Arvind Kumar Sharma; Yogendra Sharma; Sudeb Dasgupta; Bulusu Anand (ISQED, 2015)

Timing model for two stage buffer and its application in ECSM characterization. - Yogesh Chaurasiya; Surabhi Bhargava; Arvind Kumar Sharma; Baljit Kaur; Bulusu Anand (VDAT, 2015)

Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies. - Arvind Kumar Sharma; Neeraj Mishra; Naushad Alam; Sudeb Dasgupta; Anand Bulusu (VDAT, 2015)

A novel energy-efficient self-correcting methodology employing INWE. - Chaudhry Indra Kumar; Arvind Kumar Sharma; Sandeep Miryala; Anand Bulusu (SMACD, 2016)

An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis. - Sayyaparaju Sagar Varma; Arvind Kumar Sharma; Bulusu Anand (SMACD, 2016)

A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization. - Baljit Kaur; Arvind Kumar Sharma; Naushad Alam; S. K. Manhas; Bulusu Anand (Microelectron. J., 2016)

UTBB FD-SOI Circuit Design using Multifinger Transistors: A Circuit-Device Interaction Perspective. - Arvind Kumar Sharma; Naushad Alam; Anand Bulusu (PRIME, 2018)

ALIGN: Open-Source Analog Layout Automation from the Ground Up. - Kishor Kunal; Meghna Madhusudan; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu; Desmond A. Kirkpatrick; Sachin S. Sapatnekar (DAC, 2019)

An energy-efficient variation aware self-correcting latch. - Chaudhry Indra Kumar; Arvind Kumar Sharma; Rajendra Partap; Anand Bulusu (Microelectron. J., 2019)

A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches. - Chaudhry Indra Kumar; Ishant Bhatia; Arvind Kumar Sharma; Deep Sehgal; H. S. Jatana; Anand Bulusu (IEEE Trans. Very Large Scale Integr. Syst., 2019)

GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. - Kishor Kunal; Tonmoy Dhar; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Jiang Hu; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2020)

The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Yishuang Lin; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Soner Yaldiz; et al. (ICCAD, 2020)

A Customized Graph Neural Network Model for Guiding Analog IC Placement. - Yaguang Li; Yishuang Lin; Meghna Madhusudan; Arvind K. Sharma; Wenbin Xu; Sachin S. Sapatnekar; Ramesh Harjani; Jiang Hu (ICCAD, 2020)

Learning from Experience: Applying ML to Analog Circuit Design. - Kishor Kunal; Tonmoy Dhar; Yaguang Li; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Sachin S. Sapatnekar (ISPD, 2020)

Exploring a Machine Learning Approach to Performance Driven Analog IC Placement. - Yaguang Li; Yishuang Lin; Meghna Madhusudan; Arvind K. Sharma; Wenbin Xu; Sachin S. Sapatnekar; Ramesh Harjani; Jiang Hu (ISVLSI, 2020)

Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. - Tonmoy Dhar; Jitesh Poojary; Yaguang Li; Kishor Kunal; Meghna Madhusudan; Arvind K. Sharma; Susmita Dey Manasi; Jiang Hu; Ramesh Harjani; Sachin S. Sapatnekar (ASP-DAC, 2021)

Analog Layout Generation using Optimized Primitives. - Meghna Madhusudan; Arvind K. Sharma; Yaguang Li; Jiang Hu; Sachin S. Sapatnekar; Ramesh Hajiani (DATE, 2021)

Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. - Arvind K. Sharma; Meghna Madhusudan; Steven M. Burns; Parijat Mukherjee; Soner Yaldiz; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2021)

From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. - Juzheng Liu; Shiyu Su; Meghna Madhusudan; Mohsen Hassanpourghadi; Samuel Saunders; Qiaochu Zhang; Rezwan A. Rasul; Yaguang Li; Jiang Hu; Arvind Kumar Sharma; Sachin S. Sapatnekar; Ramesh Harjani; et al. (ICCAD, 2021)

Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. - Arvind K. Sharma; Meghna Madhusudan; Steven M. Burns; Soner Yaldiz; Parijat Mukherjee; Ramesh Harjani; Sachin S. Sapatnekar (ICCAD, 2021)

Machine Learning Techniques in Analog Layout Automation. - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Yishuang Lin; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Soner Yaldiz; et al. (ISPD, 2021)

Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization. - Lomash Chandra Acharya; Arvind Kumar Sharma; Venkatraman Ramakrishnan; Ajoy Mandal; Sudeb Dasgupta; Anand Bulusu (ISQED, 2021)

A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing. - Yaguang Li; Yishuang Lin; Meghna Madhusudan; Arvind K. Sharma; Sachin S. Sapatnekar; Ramesh Harjani; Jiang Hu (MLCAD, 2021)

ALIGN: A System for Automating Analog Layout. - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu; Desmond A. Kirkpatrick; Parijat Mukherjee; et al. (IEEE Des. Test, 2021)

Automation Monitoring With Sensors For Detecting Covid Using Backpropagation Algorithm. - Pravin Kshirsagar; Hariprasath Manoharan; Vineet Tirth; Mohd Naved; Ahmad Tasnim Siddiqui; Arvind K. Sharma (KSII Trans. Internet Inf. Syst., 2021)

Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead. - Nibedita Karmokar; Meghna Madhusudan; Arvind K. Sharma; Ramesh Harjani; Mark Po-Hung Lin; Sachin S. Sapatnekar (ASP-DAC, 2022)

Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays. - Nibedita Karmokar; Arvind K. Sharma; Jitesh Poojary; Meghna Madhusudan; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2022)

Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. - Ramprasath S 001; Meghna Madhusudan; Arvind K. Sharma; Jitesh Poojary; Soner Yaldiz; Ramesh Harjani; Steven M. Burns; Sachin S. Sapatnekar (ISPD, 2022)

An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime. - Mahipal Dargupally; Lomash Chandra Acharya; Khoirom Johnson Singh; Neha Gupta; Arvind K. Sharma; Sudeb Dasgupta; Anand Bulusu (APCCAS, 2023)

AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells. - Sumanth Kamineni; Arvind K. Sharma; Ramesh Harjani; Sachin S. Sapatnekar; Benton H. Calhoun (DATE, 2023)

Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology. - Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Ramprasath S 001; Kishor Kunal; Sachin S. Sapatnekar; Ramesh Harjani (ESSDERC, 2023)

Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure. - Lomash Chandra Acharya; Anubhav Kumar; Khoirom Johnson Singh; Neha Gupta; Nayakanti Sai Shabarish; Neeraj Mishra; Mahipal Dargupally; Arvind Kumar Sharma; Venkatraman Ramakrishnan; Ajoy Mandal; Sudeb Dasgupta; Anand Bulusu (SMACD, 2023)

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort. - Lomash Chandra Acharya; Arvind Kumar Sharma; Neeraj Mishra; Khoirom Johnson Singh; Mahipal Dargupally; Nayakanti Sai Shabarish; Ajoy Mandal; Venkatraman Ramakrishnan; Sudeb Dasgupta; Anand Bulusu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Performance-driven Wire Sizing for Analog Integrated Circuits. - Yaguang Li; Yishuang Lin; Meghna Madhusudan; Arvind K. Sharma; Sachin S. Sapatnekar; Ramesh Harjani; Jiang Hu (ACM Trans. Design Autom. Electr. Syst., 2023)

Addressing image and Poisson noise deconvolution problem using deep learning approaches. - Mohammad Haider Syed; Kamal Upreti; Mohammad Shahnawaz Nasir; Mohammad Shabbir Alam; Arvind Kumar Sharma (Comput. Intell., 2023)

Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs. - Nibedita Karmokar; Arvind K. Sharma; Jitesh Poojary; Meghna Madhusudan; Ramesh Harjani; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

GNN-Based Hierarchical Annotation for Analog Circuits. - Kishor Kunal; Tonmoy Dhar; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Jiang Hu; Ramesh Harjani; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. - Ramprasath Srinivasa Gopalakrishnan; Meghna Madhusudan; Arvind K. Sharma; Jitesh Poojary; Soner Yaldiz; Ramesh Harjani; Steven M. Burns; Sachin S. Sapatnekar (ACM Trans. Design Autom. Electr. Syst., 2023)

Reinforcing the Connection between Analog Design and EDA (Invited Paper). - Kishor Kunal; Meghna Madhusudan; Jitesh Poojary; S. Ramprasath 001; Arvind K. Sharma; Ramesh Harjani; Sachin S. Sapatnekar (ASPDAC, 2024)

Essence of Internet of Medical Things in Geriatric Healthcare. - Ananya Mahajan; Parini Jindal; Arvind K. Sharma; Rajinder Kaur (ICCCNT, 2024)

Show Me the World in My Language: Establishing the First Baseline for Scene-Text to Scene-Text Translation. - Shreyas Vaidya; Arvind Kumar Sharma; Prajwal Gatti; Anand Mishra 001 (ICPR (30), 2024)

Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis. - Lomash Chandra Acharya; Arvind K. Sharma; Neeraj Mishra; Khoirom Johnson Singh; Mahipal Dargupally; Neha Gupta; Nayakanti Sai Shabarish; Ajoy Mandal; Venkatraman Ramakrishnan; Sudeb Dasgupta; Anand Bulusu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients. - Arvind K. Sharma; Meghna Madhusudan; Steven M. Burns; Soner Yaldiz; Parijat Mukherjee; Ramesh Harjani; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A Methodology for Datapath Energy Prediction and Optimization in Near Threshold Voltage Regime. - Mahipal Dargupally; Lomash Chandra Acharya; Arvind K. Sharma; Sudeb Dasgupta; Anand Bulusu (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Robust and Reliable Energy-Efficient Level Shifter. - Mahipal Dargupally; Lomash Chandra Acharya; Neha Gupta; Ahrron Kongala; Arvind K. Sharma; Sudeb Dasgupta; Anand Bulusu (IEEE Trans. Circuits Syst. II Express Briefs, 2025)