nterface Synthesis: Issues and Approaches. - Arvind Rajawat; M. Balakrishnan; Anshul Kumar (VLSI Design, 2000)

Dominant block guided optimal cache size estimation to maximize IPC of embedded software. - Rajendra Patel; Arvind Rajawat (CoRR, 2013)

A Survey of Embedded Software Profiling Methodologies. - Rajendra Patel; Arvind Rajawat (CoRR, 2013)

Recent trends in embedded system software performance estimation. - Rajendra Patel; Arvind Rajawat (Des. Autom. Embed. Syst., 2013)

Instruction cache design space exploration for embedded software applications. - Rajendra Patel; Arvind Rajawat (VDAT, 2015)

A Case Study: Task Scheduling Methodologies for High Speed Computing Systems. - Mahendra Vucha; Arvind Rajawat (CoRR, 2015)

Dynamic Task Distribution Model for On-Chip Reconfigurable High Speed Computing System. - Mahendra Vucha; Arvind Rajawat (Int. J. Reconfigurable Comput., 2015)

Performance evaluation of circuit level approaches for radiation hardened primitive gates. - Vaibhav Sharma 006; Arvind Rajawat (ICACCI, 2016)

Area and Throughput Analysis of Different AES Architectures for FPGA Implementations. - Disha Yadav; Arvind Rajawat (iNIS, 2016)

Fast and efficient power estimation model for FPGA based designs. - Abhishek N. Tripathi 001; Arvind Rajawat (Microprocess. Microsystems, 2018)

Fast and Accurate System-Level Power Estimation Model for FPGA-Based Designs. - Abhishek N. Tripathi 001; Arvind Rajawat (J. Circuits Syst. Comput., 2019)

An Accurate and Quick ANN-Based System-Level Dynamic Power Estimation Model Using LLVM IR Profiling for FPGA Designs. - Abhishek N. Tripathi 001; Arvind Rajawat (IEEE Embed. Syst. Lett., 2020)

Statistical traffic pattern for mixed torus topology and pathfinder based traffic and thermal aware routing protocol on NoC. - Ashish Valuskar; Madhu Shandilya; Arvind Rajawat (Integr., 2022)

FPGA implementation of PUF based key generator for secure communication in IoT. - Amol K. Boke; Sangeeta Nakhate; Arvind Rajawat (Integr., 2023)