Automatic place-and-route of emerging LED-driven wires within a monolithically-integrated CMOS-III-V process. - Tushar Krishna; Arya Balachandran; Siau Ben Chiah; Li Zhang; Bing Wang; Cong Wang; Kenneth Eng-Kian Lee; Jürgen Michel; Li-Shiuan Peh (DATE, 2017)

A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS. - Arya Balachandran; Yong Chen 005; Chirn Chye Boon (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS. - Arya Balachandran; Yong Chen 005; Chirn Chye Boon (APCCAS, 2019)