A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS. - Samir Parikh; Tony Kao; Yasuo Hidaka; Jian Jiang; Asako Toda; Scott McLeod; William W. Walker; Yoichi Koyanagi; Toshiyuki Shibuya; Jun Yamada (ISSCC, 2013)

22.2 A 25Gb/s hybrid integrated silicon photonic transceiver in 28nm CMOS and SOI. - Yanfei Chen; Masaya Kibune; Asako Toda; Akinori Hayakawa; Tomoyuki Akiyama; Shigeaki Sekiguchi; Hiroji Ebe; Nobuhiro Imaizumi; Tomoyuki Akahoshi; Suguru Akiyama; Shinsuke Tanaka; Takasi Simoyama; et al. (ISSCC, 2015)

A 25 Gbps silicon photonic transmitter and receiver with a bridge structure for CPU interconnects. - Akinori Hayakawa; Masaya Kibune; Asako Toda; Shinsuke Tanaka; Takasi Simoyama; Yanfei Chen; Tomoyuki Akiyama; Shigekazu Okumura; Takeshi Baba; Tomoyuki Akahoshi; Seiji Ueno; Kazunori Maruyama; et al. (OFC, 2015)

8 Tbps Co-Packaged FPGA and Silicon Photonics Optical IO. - Kaveh Hosseini; Edwin Kok; Sergey Y. Shumarayev; Chia-Pin Chiu; Arnab Sarkar 004; Asako Toda; Yanjing Ke; Allen Chan; Daniel Jeong; Mason Zhang; Sangeeta Raman; Thungoc Tran; et al. (OFC, 2021)

5.12 Tbps Co-Packaged FPGA and Silicon Photonics Interconnect I/O. - Kaveh Hosseini; Edwin Kok; Sergey Y. Shumarayev; Daniel Jeong; Allen Chan; Austin Katzin; Songtao Liu; Radek Roucka; Manan Raval; Minh Mac; Chia-Pin Chiu; Thungoc Tran; et al. (VLSI Technology and Circuits, 2022)