A new FPGA-based postprocessor architecture for channel mismatch correction of time interleaved ADCS. - Asgar Abbaszadeh; Khosrov Dabbagh-Sadeghipour (SiPS, 2009)

A new hardware efficient reconfigurable fir filter architecture suitable for FPGA applications. - Asgar Abbaszadeh; Anasystem Azerbaijan; Khosrov Dabbagh-Sadeghipour (DSP, 2011)

Efficient realization of reconfigurable FIR filter using the new coefficient representation. - Khosrov Dabbagh-Sadeghipour; Asgar Abbaszadeh (IEICE Electron. Express, 2011)

Low complexity digital background calibration algorithm for the correction of timing mismatch in time-interleaved ADCs. - Asgar Abbaszadeh; Esmaeil Najafi Aghdam; Alfredo Rosado Muñoz (Microelectron. J., 2019)