Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation. - Ritu Singhal; Asha Balijepalli; Anupama R. Subramaniam; Frank Liu 001; Sani R. Nassif; Yu Cao 001 (DAC, 2007)

Compact modeling of carbon nanotube transistor for early stage process-design exploration. - Asha Balijepalli; Saurabh Sinha; Yu Cao (ISLPED, 2007)

Compact Modeling of a PD SOI MESFET for Wide Temperature Designs. - Asha Balijepalli; Joseph Ervin; Yu Cao 001; Trevor Thornton (ISQED, 2007)

A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design. - Saurabh Sinha; Asha Balijepalli; Yu Cao (ISQED, 2008)

The Predictive Technology Model in the Late Silicon Era and Beyond. - Yu Cao 001; Asha Balijepalli; Saurabh Sinha; Chi-Chao Wang; Wenping Wang 004; Wei Zhao (Found. Trends Electron. Des. Autom., 2009)

Compact modeling of a PD SOI MESFET for wide temperature designs. - Asha Balijepalli; Joseph Ervin; William Lepkowski; Yu Cao 001; Trevor J. Thornton (Microelectron. J., 2009)

Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation. - Ritu Singhal; Asha Balijepalli; Anupama R. Subramaniam; Chi-Chao Wang; Frank Liu 001; Sani R. Nassif; Yu Cao 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)