A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR. - Jian Pang; Zheng Li 021; Ryo Kubozoe; Xueting Luo; Rui Wu 001; Yun Wang 008; Dongwon You; Ashbir Aviat Fadila; Rattanan Saengchan; Takeshi Nakamura; Joshua Alvin; Daiki Matsumoto; et al. (ISSCC, 2019)

A 28GHz CMOS Differential Bi-Directional Amplifier for 5G NR. - Zheng Li 021; Jian Pang; Ryo Kubozoe; Xueting Luo; Rui Wu 001; Yun Wang 008; Dongwon You; Ashbir Aviat Fadila; Joshua Alvin; Bangan Liu; Zheng Sun 001; Hongye Huang; et al. (ASP-DAC, 2020)

A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation. - Jian Pang; Zheng Li 021; Xueting Luo; Joshua Alvin; Rattanan Saengchan; Ashbir Aviat Fadila; Kiyoshi Yanagisawa; Yi Zhang 092; Zixin Chen; Zhongliang Huang; Xiaofan Gu; Rui Wu 001; et al. (VLSI Circuits, 2020)

A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR. - Jian Pang; Zheng Li 021; Ryo Kubozoe; Xueting Luo; Rui Wu 001; Yun Wang 008; Dongwon You; Ashbir Aviat Fadila; Rattanan Saengchan; Takeshi Nakamura; Joshua Alvin; Daiki Matsumoto; et al. (IEEE J. Solid State Circuits, 2020)

A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS. - Yun Wang 008; Rui Wu 001; Jian Pang; Dongwon You; Ashbir Aviat Fadila; Rattanan Saengchan; Xi Fu; Daiki Matsumoto; Takeshi Nakamura; Ryo Kubozoe; Masaru Kawabuchi; Bangan Liu; et al. (IEEE J. Solid State Circuits, 2020)

22.2 A 300GHz-Band Phased-Array Transceiver Using Bi-Directional Outphasing and Hartley Architecture in 65nm CMOS. - Ibrahim Abdo; Carrel da Gomez; Chun Wang; Kota Hatano; Qi Li; Chenxin Liu; Kiyoshi Yanagisawa; Ashbir Aviat Fadila; Jian Pang; Hiroshi Hamada; Hideyuki Nosaka; Atsushi Shirane; et al. (ISSCC, 2021)

A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems. - Jian Pang; Zheng Li 021; Xueting Luo; Joshua Alvin; Rattanan Saengchan; Ashbir Aviat Fadila; Kiyoshi Yanagisawa; Yi Zhang 092; Zixin Chen; Zhongliang Huang; Xiaofan Gu; Rui Wu 001; et al. (IEEE J. Solid State Circuits, 2021)

A 3.4mW/element Radiation-Hardened Ka-Band CMOS Phased-Array Receiver Utilizing Magnetic-Tuning Phase Shifter for Small Satellite Constellation. - Xi Fu; Yun Wang 008; Dongwon You; Xiaolin Wang; Ashbir Aviat Fadila; Yi Zhang 092; Sena Kato; Chun Wang; Zheng Li 021; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (ISSCC, 2022)

A Power-Efficient 24-to-71 GHz CMOS Phased-Array Receiver Utilizing Harmonic-Selection Technique Supporting 36dB Inter-Band Blocker Rejection for 5G NR. - Jian Pang; Yi Zhang 092; Zheng Li 021; Minzhe Tang; Yijing Liao; Ashbir Aviat Fadila; Atsushi Shirane; Kenichi Okada 001 (ISSCC, 2022)

A 28-GHz Fully-Passive Retro-Reflective Phased-Array Backscattering Transceiver for 5G Network with 24-GHz Beam-Steered Wireless Power Transfer. - Michihiro Ide; Yuasa Keito; Sena Kato; Dongwon You; Ashbir Aviat Fadila; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (VLSI Technology and Circuits, 2022)

A Bi-Directional 300-GHz-Band Phased-Array Transceiver in 65-nm CMOS With Outphasing Transmitting Mode and LO Emission Cancellation. - Ibrahim Abdo; Carrel da Gomez; Chun Wang; Kota Hatano; Qi Li; Chenxin Liu; Kiyoshi Yanagisawa; Ashbir Aviat Fadila; Takuya Fujimura; Tsuyoshi Miura; Korkut Kaan Tokgoz; Jian Pang; et al. (IEEE J. Solid State Circuits, 2022)

A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal. - Yun Wang 008; Dongwon You; Xi Fu; Takeshi Nakamura; Ashbir Aviat Fadila; Teruki Someya; Atsuhiro Kawaguchi; Junjun Qiu; Jian Pang; Kiyoshi Yanagisawa; Bangan Liu; Yuncheng Zhang; et al. (IEEE J. Solid State Circuits, 2022)

A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24-71-GHz Utilizing Harmonic-Selection Technique With 36-dB Inter-Band Blocker Tolerance for 5G NR. - Yi Zhang 092; Jian Pang; Zheng Li 021; Minzhe Tang; Yijing Liao; Ashbir Aviat Fadila; Atsushi Shirane; Kenichi Okada 001 (IEEE J. Solid State Circuits, 2022)

A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference. - Dingxin Xu; Yuncheng Zhang; Hongye Huang; Zheng Sun 001; Bangan Liu; Ashbir Aviat Fadila; Junjun Qiu; Zezheng Liu; Wenqian Wang; Yuang Xiong; Waleed Madany; Atsushi Shirane; et al. (CICC, 2023)

A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path. - Waleed Madany; Yuncheng Zhang; Ashbir Aviat Fadila; Hongye Huang; Junjun Qiu; Atsushi Shirane; Kenichi Okada 001 (ESSCIRC, 2023)

A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low-Earth-Orbit Small Satellite Constellation. - Xi Fu; Dongwon You; Xiaolin Wang; Michihiro Ide; Yuncheng Zhang; Jun Sakamaki; Ashbir Aviat Fadila; Zheng Li 021; Yun Wang 008; Jumpei Sudo; Makoto Higaki; Soichiro Inoue; et al. (ISSCC, 2023)

A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration. - Junjun Qiu; Wenqian Wang; Zheng Sun 001; Bangan Liu; Yuncheng Zhang; Dingxin Xu; Hongye Huang; Ashbir Aviat Fadila; Zezheng Liu; Waleed Madany; Yuang Xiong; Atsushi Shirane; et al. (ISSCC, 2023)

A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler. - Dongwon You; Xi Fu; Xiaolin Wang; Yuan Gao; Wenqian Wang; Jun Sakamaki; Hans Herdian; Sena Kato; Michihiro Ide; Yuncheng Zhang; Ashbir Aviat Fadila; Zheng Li 021; et al. (ISSCC, 2023)

A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Transformer Combined FIR FIlter. - Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Junjun Qiu; Dingxin Xu; Yi Zhang 092; Xi Fu; Dongwon You; Hongye Huang; Waleed Madany; Ashbir Aviat Fadila; Zezheng Liu; et al. (VLSI Technology and Circuits, 2023)

A Low-Power 256-Element Ka-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small Satellite Constellations. - Xi Fu; Dongwon You; Xiaolin Wang; Yun Wang 008; Carolyn Jill Mayeda; Yuan Gao; Michihiro Ide; Yuncheng Zhang; Jun Sakamaki; Ashbir Aviat Fadila; Zheng Li 021; Jumpei Sudo; et al. (IEEE J. Solid State Circuits, 2023)

300-GHz-Band InP HBT Power Amplifier and InP-CMOS Hybrid Phased-Array Transmitter. - Teruo Jyo; Ibrahim Abdo; Hiroshi Hamada; Munehiko Nagatani; Adam Pander; Hitoshi Wakita; Miwa Mutoh; Yuta Shiratori; Daisuke Kitayama; Carrel da Gomez; Chun Wang; Kota Hatano; et al. (BCICTS, 2024)

10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter. - Dingxin Xu; Zezheng Liu; Yifeng Kuai; Hongye Huang; Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Wenqian Wang; Yuang Xiong; Junjun Qiu; Waleed Madany; Yi Zhang 092; et al. (ISSCC, 2024)

A synthesizable spread spectrum clock generator based on type-II/III fractional-N DPLL. - Waleed Madany; Hongye Huang; Bangan Liu; Ashbir Aviat Fadila; Zezheng Liu; Wenqian Wang; Junjun Qiu; Jill C. Mayeda; Atsushi Shirane; Kenichi Okada 001 (IEICE Electron. Express, 2024)

A Low-Power Radiation-Hardened Ka-Band CMOS Phased-Array Receiver for Small Satellite Constellation. - Xi Fu; Dongwon You; Yun Wang 008; Xiaolin Wang; Ashbir Aviat Fadila; Chenxin Liu; Sena Kato; Chun Wang; Zheng Li 021; Jian Pang; Atsushi Shirane; Kenichi Okada 001 (IEEE J. Solid State Circuits, 2024)

A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter. - Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Junjun Qiu; Dingxin Xu; Yi Zhang 092; Xi Fu; Dongwon You; Hongye Huang; Waleed Madany; Ashbir Aviat Fadila; Zezheng Liu; et al. (IEEE J. Solid State Circuits, 2024)

A 6.65-to-7.75GHz Fractional-N Digital PLL with Analog Pre-Distortion DTC Implementing 2nd/3rd-Order Calibration and Achieving -65.7dBc Fractional Spur and 154fs Integrated Jitter. - Daxu Zhang; Dingxin Xu; Hongye Huang; Waleed Madany; Zezheng Liu; Wenqian Wang; Yuang Xiong; Ashbir Aviat Fadila; Duo Li; Yuncheng Zhang; Atsushi Shirane; Kenichi Okada 001 (CICC, 2025)

5.6 A Power-Efficient CORDIC-Less Digital Polar Transmitter Using 1b DSM-Based PA Supporting 256-QAM. - Yuncheng Zhang; Zezheng Liu; Duo Li; Minzhe Tang; Yi Zhang 092; Hongye Huang; Dingxin Xu; Waleed Madany; Ashbir Aviat Fadila; Wenqian Wang; Yuang Xiong; Daxu Zhang; et al. (ISSCC, 2025)

NLJM: A Simplified Jitter Model of Digital Standard Cells for Rapid Automatic Design of Frequency Synthesizers. - Hongye Huang; Ashbir Aviat Fadila; Dingxin Xu; Waleed Madany; Wenqian Wang; Zezheng Liu; Yuang Xiong; Tianshi Hu; Bangan Liu; Yuncheng Zhang; Atsushi Shirane; Kenichi Okada 001 (IEEE Access, 2025)

A 0.8-1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation. - Waleed Madany; Yuncheng Zhang; Ashbir Aviat Fadila; Hongye Huang; Junjun Qiu; Jill C. Mayeda; Atsushi Shirane; Kenichi Okada 001 (IEEE Access, 2025)

A LEO Satellite Mounted 256-Element 19 GHz CMOS Phased-Array Transmitter With On-Chip Amplitude and Phase Monitor. - Xiaolin Wang; Dongwon You; Xi Fu; Gao Yuan; Takeshi Ota; Jill C. Mayeda; Jun Sakamaki; Ashbir Aviat Fadila; Makoto Higaki; Jumpei Sudo; Hiroshi Takizawa; Masashi Shirakura; et al. (IEEE Access, 2025)

A 6.5-to-8-GHz Cascaded Dual-Fractional-N Digital PLL Achieving -52.79-dBc Fractional Spur With 50-MHz Reference. - Dingxin Xu; Yuncheng Zhang; Hongye Huang; Zheng Sun 001; Bangan Liu; Ashbir Aviat Fadila; Junjun Qiu; Zezheng Liu; Wenqian Wang; Yuang Xiong; Waleed Madany; Atsushi Shirane; et al. (IEEE J. Solid State Circuits, 2025)

A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a - 62.1-dBc Fractional Spur. - Dingxin Xu; Zezheng Liu; Yifeng Kuai; Hongye Huang; Yuncheng Zhang; Zheng Sun 001; Bangan Liu; Wenqian Wang; Yuang Xiong; Junjun Qiu; Waleed Madany; Yi Zhang 092; et al. (IEEE J. Solid State Circuits, 2025)