High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension. - Rishan Senanayake; Namitha Liyanage; Sasindu Wijeratne; Sachille Atapattu; Kasun Athukorala; P. M. K. Tharaka; Geethan Karunaratne; R. M. A. U. Senarath; Ishantha Perera; Ashen Ekanayake; Ajith Pasqual (ASAP, 2017)

Scalable High Performance SDN Switch Architecture on FPGA for Core Networks. - Sasindu Wijeratne; Ashen Ekanayake; Sandaruwan Jayaweera; Danuka Ravishan; Ajith Pasqual (FPGA, 2019)

Virtual-Link: A Scalable Multi-Producer Multi-Consumer Message Queue Architecture for Cross-Core Communication. - Qinzhe Wu; Jonathan Beard; Ashen Ekanayake; Andreas Gerstlauer; Lizy K. John (IPDPS, 2021)

SPAMeR: Speculative Push for Anticipated Message Requests in Multi-Core Systems. - Qinzhe Wu; Ashen Ekanayake; Ruihao Li 002; Jonathan Beard; Lizy Kurian John (ICPP, 2022)

SecurityCloak: Protection against cache timing and speculative memory access attacks. - Fernando Mosquera; Ashen Ekanayake; William Hua; Krishna Kavi; Gayatri Mehta; Lizy Kurian John (J. Syst. Archit., 2024)