Analog sampled data architecture for discrete Hartley transform for prime N. - Ashis Kumar Mal; Anindya Sundar Dhar (ICECS, 2003)

A generalized analog architecture for DCT, DST and its inverse. - Ashis Kumar Mal; Arindam Basu (ICASSP (5), 2004)

Digital controlled analog architecture for DCT and DST using capacitor switching. - Arindam Basu; Ashis Kumar Mal; Anindya Sundar Dhar (ISCAS (2), 2004)

Sampled analog architecture for DCT and DST. - Ashis Kumar Mal; Arindam Basu; Anindya Sundar Dhar (ISCAS (2), 2004)

Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors. - Ashis Kumar Mal; Anindya Sundar Dhar (VLSI Design, 2004)

Interconnect Slew Metric Using Nakagami-M Distribution. - Shainky Gupta; Anuran Chattaraj; Rajib Kar; Ashish Kumar Mal (ICETET, 2008)

Delay Estimation for On-Chip VLSI Interconnect using Weibull Distribution Function. - Rajib Kar; Anuran Chattaraj; Aniruddha Chandra; Ashis Kumar Mal; A. K. Bhattacharjee (ICIIS, 2008)

Design of DXT architecture using current switched integrator. - Ashis Kumar Mal; Om Prakash Hari; Rishi Todani; Anindya Sundar Dhar (APCCAS, 2010)

A Closed Form Slew Evaluation Approach Using Burr's Distribution Function for High Speed On-Chip RC Interconnects. - Rajib Kar; Vikas Maheshwari; Md. Maqbool; Ashish Kumar Mal; A. K. Bhattacharjee (BAIP, 2010)

Impact of Burst Assembly Algorithms on Data Loss in OBS Networks Under Time-Correlated Traffic Input. - Subhrabrata Choudhury; Gargi Chakraborty; Ashish Kumar Mal (JOCN, 2010)

Coercion Resistant MIX for Electronic Auction. - Jaydeep Howlader; Jayanta Kar; Ashis Kumar Mal (ICISS, 2012)

Routing Scheme for OBS Networks. - Subhrabrata Choudhury; Vivek Nair; Ashis Kumar Mal (JOCN, 2012)

A power efficient and digitally assisted CMOS complementary telescopic amplifier with wide input common mode range. - Rishi Todani; Ashis Kumar Mal (ISQED, 2013)

Practical Receipt-Free Sealed-Bid Auction in the Coercive Environment. - Jaydeep Howlader; Sanjit Kumar Roy; Ashis Kumar Mal (IACR Cryptol. ePrint Arch., 2014)

An integrated routing and offset-time adaptation scheme for OBS network. - Subhrabrata Choudhury; Vivek Nair; Jaydeep Howlader; B. Choudhury; Ashis Kumar Mal (ICDCN, 2015)

Analysis of resistive load ring oscillator. - Saurav Mandal; Ashis Kumar Mal (ReTIS, 2015)

Sealed-bid auction: a cryptographic solution to bid-rigging attack in the collusive environment. - Jaydeep Howlader; Ashis Kumar Mal (Secur. Commun. Networks, 2015)

Optimal Location of Energy Efficient DF Relay Node in κ - μ Fading Channel. - Biswajit Ghosh; Aniruddha Chandra; Ashis Kumar Mal (Wirel. Pers. Commun., 2017)

Performance enhancement of a VCO using symbolic modelling and optimisation. - Madhusmita Panda; Santosh Kumar Patnaik; Ashis Kumar Mal (IET Circuits Devices Syst., 2018)

A cost-effective system for triggering alarm to distracted drivers/ nurses. - Debabrata Bej; Subhajit Rakshit; Ashis Kumar Mal; Rajat Mahapatra (Comput. Electr. Eng., 2019)

Optimal design of complementary metal-oxide-semiconductor analogue circuits: An evolutionary approach. - Sumalya Ghosh; Bishnu Prasad De; Rajib Kar; Durbadal Mandal; Ashis Kumar Mal (Comput. Electr. Eng., 2019)

Symbiotic organisms search algorithm for optimal design of CMOS two-stage op-amp with nulling resistor and robust bias circuit. - Sumalya Ghosh; Bishnu Prasad De; Rajib Kar; Ashis Kumar Mal (IET Circuits Devices Syst., 2019)

Fast and optimised design of a differential VCO using symbolic technique and multi objective algorithms. - Madhusmita Panda; Santosh Kumar Patnaik; Ashis Kumar Mal; Sumalya Ghosh (IET Circuits Devices Syst., 2019)

All MOS noise-shaped time-mode temperature sensor. - R. S. S. M. R. Krishna; Ashis Kumar Mal; Rajat Mahapatra (Integr., 2019)

An Efficient NoC-based ANN Framework for Epileptic Seizure Recognition. - Ayut Ghosh; Arka Prava Roy; Ramapati Patra; Ashis Kumar Mal; Hemanta Kumar Mondal (iSES, 2020)

Time-Domain Smart Temperature Sensor Using Current Starved Inverters and Switched Ring Oscillator-Based Time-to-Digital Converter. - R. S. S. M. R. Krishna; Ashis Kumar Mal; Rajat Mahapatra (Circuits Syst. Signal Process., 2020)

Optimal Design of Ultra-Low-Power 2.4 GHz LNA for IEEE 802.15.4/Bluetooth Applications. - Sumalya Ghosh; Bishnu Prasad De; Kanchan Baran Maji; Rajib Kar; Durbadal Mandal; Ashis Kumar Mal (J. Circuits Syst. Comput., 2020)

Performance of an Adaptive Cooperative NOMA Scheme with Transmit Antenna Selection. - Amrita Mukherjee; Pratik Chakraborty; Shankar Prakriya; Ashis Kumar Mal (ANTS, 2021)

A cost-effective alertness-rating tool to enable situational awareness among on-duty static security guards in Covid-19 pandemic. - Debabrata Bej; Shubhranil Chakraborty; Sekh Arif Mahammad; Ashis Kumar Mal (J. Reliab. Intell. Environ., 2021)

Fuzzy Logic-Based Energy-Optimal Collinear DF Relay Placement in Two-Hop η -μ Fading Channel. - Biswajit Ghosh; Aniruddha Chandra; Ashis Kumar Mal (Int. J. Wirel. Inf. Networks, 2022)

Cooperative Mode Switching-Based Cognitive NOMA With Transmit Antenna and User Selection. - Amrita Mukherjee; Pratik Chakraborty; Shankar Prakriya; Ashis Kumar Mal (IEEE Trans. Signal Inf. Process. over Networks, 2022)

Performance of Novel Adaptive Schemes for Cognitive Full-Duplex Relaying-Based Downlink Cooperative NOMA. - Amrita Mukherjee; Pratik Chakraborty; Shankar Prakriya; Ashis Kumar Mal (IEEE Trans. Wirel. Commun., 2023)

A Survey on Hardware Accelerator Design of Deep Learning for Edge Devices. - Anu Samanta; Indranil Hatai; Ashis Kumar Mal (Wirel. Pers. Commun., 2024)