Empirical failure analysis and validation of fault models in CMOS VLSI. - Ashish Pancholy; Janusz Rajski; Larry J. McNaughton (ITC, 1990)

Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits. - Ashish Pancholy; Janusz Rajski; Larry J. McNaughton (IEEE Des. Test Comput., 1992)

Yield and matching implications for static RAM memory array sense-amplifier design. - Simon J. Lovett; Gary A. Gibbs; Ashish Pancholy (IEEE J. Solid State Circuits, 2000)