ASLAN: Synthesis of approximate sequential circuits. - Ashish Ranjan 001; Arnab Raha; Swagath Venkataramani; Kaushik Roy 001; Anand Raghunathan (DATE, 2014)

AxNN: energy-efficient neuromorphic systems using approximate computing. - Swagath Venkataramani; Ashish Ranjan 001; Kaushik Roy 001; Anand Raghunathan (ISLPED, 2014)

Approximate storage for energy efficient spintronic memories. - Ashish Ranjan 001; Swagath Venkataramani; Xuanyao Fong; Kaushik Roy 001; Anand Raghunathan (DAC, 2015)

DyReCTape: a dynamically reconfigurable cache using domain wall memory tapes. - Ashish Ranjan 001; Shankar Ganesh Ramasubramanian; Rangharajan Venkatesan; Vijay S. Pai; Kaushik Roy 001; Anand Raghunathan (DATE, 2015)

STAxCache: An approximate, energy efficient STT-MRAM cache. - Ashish Ranjan 001; Swagath Venkataramani; Zoha Pajouhi; Rangharajan Venkatesan; Kaushik Roy 001; Anand Raghunathan (DATE, 2017)

ScaleDeep: A Scalable Compute Architecture for Learning and Evaluating Deep Networks. - Swagath Venkataramani; Ashish Ranjan 001; Subarno Banerjee; Dipankar Das 002; Sasikanth Avancha; Ashok Jagannathan; Ajaya Durg; Dheemanth Nagaraj; Bharat Kaul; Pradeep Dubey; Anand Raghunathan (ISCA, 2017)

Approximate memory compression for energy-efficiency. - Ashish Ranjan 001; Arnab Raha; Vijay Raghunathan; Anand Raghunathan (ISLPED, 2017)

AxBA: an approximate bus architecture framework. - Jacob R. Stevens; Ashish Ranjan 001; Anand Raghunathan (ICCAD, 2018)

Computing in Memory With Spin-Transfer Torque Magnetic RAM. - Shubham Jain; Ashish Ranjan 001; Kaushik Roy 001; Anand Raghunathan (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Automatic Synthesis Techniques for Approximate Circuits. - Ashish Ranjan 001; Swagath Venkataramani; Shubham Jain; Younghoon Kim; Shankar Ganesh Ramasubramanian; Arnab Raha; Kaushik Roy 001; Anand Raghunathan (Approximate Circuits, 2019)

X-MANN: A Crossbar based Architecture for Memory Augmented Neural Networks. - Ashish Ranjan 001; Shubham Jain; Jacob R. Stevens; Dipankar Das 002; Bharat Kaul; Anand Raghunathan (DAC, 2019)

Manna: An Accelerator for Memory-Augmented Neural Networks. - Jacob R. Stevens; Ashish Ranjan 001; Dipankar Das 002; Bharat Kaul; Anand Raghunathan (MICRO, 2019)

Emerging Neural Workloads and Their Impact on Hardware. - David Brooks 001; Martin M. Frank; Tayfun Gokmen; Udit Gupta; Xiaobo Sharon Hu; Shubham Jain; Ann Franchesca Laguna; Michael T. Niemier; Ian O'Connor; Anand Raghunathan; Ashish Ranjan 001; Dayane Reis; et al. (DATE, 2020)

Approximate Memory Compression. - Ashish Ranjan 001; Arnab Raha; Vijay Raghunathan; Anand Raghunathan (IEEE Trans. Very Large Scale Integr. Syst., 2020)

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. - Swagath Venkataramani; Vijayalakshmi Srinivasan; Wei Wang 333; Sanchari Sen; Jintao Zhang; Ankur Agrawal; Monodeep Kar; Shubham Jain; Alberto Mannari; Hoang Tran; Yulong Li; Eri Ogawa; et al. (ISCA, 2021)

Energy Efficient Cache Design with Piezoelectric FETs. - Reena Elangovan; Ashish Ranjan 001; Niharika Thakuria; Sumeet Kumar Gupta; Anand Raghunathan (ISLPED, 2022)

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (ISSCC, 2024)

Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (IEEE J. Solid State Circuits, 2025)