Timing-driven maze routing. - Sung-Woo Hur; Ashok Jagannathan; John Lillis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

A fast algorithm for context-aware buffer insertion. - Ashok Jagannathan; Sung-Woo Hur; John Lillis (ACM Trans. Design Autom. Electr. Syst., 2002)

Microarchitecture evaluation with physical planning. - Jason Cong; Ashok Jagannathan; Glenn Reinman; Michail Romesis (DAC, 2003)

Microarchitecture evaluation with floorplanning and interconnect pipelining. - Ashok Jagannathan; Hannah Honghua Yang; Kris Konigsfeld; Dan Milliron; Mosur Mohan; Michail Romesis; Glenn Reinman; Jason Cong (ASP-DAC, 2005)

Instruction set extension with shadow registers for configurable processors. - Jason Cong; Yiping Fan; Guoling Han; Ashok Jagannathan; Glenn Reinman; Zhiru Zhang (FPGA, 2005)

Understanding the energy efficiency of SMT and CMP with multiclustering. - Jason Cong; Ashok Jagannathan; Glenn Reinman; Yuval Tamir (ISLPED, 2005)

An automated design flow for 3D microarchitecture evaluation. - Jason Cong; Ashok Jagannathan; Yuchun Ma; Glenn Reinman; Jie Wei; Yan Zhang (ASP-DAC, 2006)

Accelerating Sequential Applications on CMPs Using Core Spilling. - Jason Cong; Guoling Han; Ashok Jagannathan; Glenn Reinman; Krzysztof Rutkowski (IEEE Trans. Parallel Distributed Syst., 2007)

Array scalarization in high level synthesis. - Preeti Ranjan Panda; Namita Sharma 001; Arun Kumar Pilania; Gummidipudi Krishnaiah; Sreenivas Subramoney; Ashok Jagannathan (ASP-DAC, 2014)

ScaleDeep: A Scalable Compute Architecture for Learning and Evaluating Deep Networks. - Swagath Venkataramani; Ashish Ranjan 001; Subarno Banerjee; Dipankar Das 002; Sasikanth Avancha; Ashok Jagannathan; Ajaya Durg; Dheemanth Nagaraj; Bharat Kaul; Pradeep Dubey; Anand Raghunathan (ISCA, 2017)