Average Power in Digital CMOS Circuits using Least Square Estimation. - Ashok K. Murugavel; N. Ranganathan; Ramamurti Chandramouli; Srinath Chavali (VLSI Design, 2001)

Power estimation of sequential circuits using hierarchical colored hardware petri net modeling. - Ashok K. Murugavel; N. Ranganathan (ISLPED, 2002)

A Real Delay Switching Activity Simulator Based on Petri Net Modeling. - Ashok K. Murugavel; N. Ranganathan (ASP-DAC/VLSI Design, 2002)

Least-square estimation of average power in digital CMOS circuits. - Ashok K. Murugavel; N. Ranganathan; Ramamurti Chandramouli; Srinath Chavali (IEEE Trans. Very Large Scale Integr. Syst., 2002)

A low power scheduler using game theory. - N. Ranganathan; Ashok K. Murugavel (CODES+ISSS, 2003)

A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. - N. Ranganathan; Ashok K. Murugavel (ICCD, 2003)

A Game-Theoretic Approach for Binding in Behavioral Synthesis. - Ashok K. Murugavel; N. Ranganathan (VLSI Design, 2003)

Petri net modeling of gate and interconnect delays for power estimation. - Ashok K. Murugavel; N. Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2003)

A game theoretic approach for power optimization during behavioral synthesis. - Ashok K. Murugavel; N. Ranganathan (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. - Ashok K. Murugavel; N. Ranganathan (VLSI Design, 2004)

Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis. - Ashok K. Murugavel; N. Ranganathan (VLSI Design, 2004)