Design of Low Power High Speed ALU Using Feedback Switch Logic. - Patanjali Prakash; Ashok Kumar Saxena (ARTCom, 2009)

Design of Low Power Adiabatic SRAM Using DTGAL, CPAL and ACPL: A Comparative Study. - Y. K. Sudharshan; D. Sreenu; Ashok K. Saxena; Sudeb Dasgupta (J. Low Power Electron., 2009)

Quantum Inversion Charge and Drain Current Analysis for Double Gate FinFET Device: Analytical Modeling and TCAD Simulation Approach. - Balwinder Raj; Ashok K. Saxena; Sudeb Dasgupta (EMS, 2010)

Robust Double Gate FinFET Based Sense Amplifier Design Using Independent Gate Control. - Surendra S. Rathod; Ashok K. Saxena; Sudeb Dasgupta (J. Low Power Electron., 2010)

A proposed DG-FinFET based SRAM cell design with RadHard capabilities. - Surendra S. Rathod; Ashok K. Saxena; Sudeb Dasgupta (Microelectron. Reliab., 2010)

Quantum Mechanical Analytical Drain Current Modeling and Simulation for Double Gate FinFET Device Using Quasi Fermi Potential Approach. - Balwinder Raj; Ashok K. Saxena; Sudeb Dasgupta (SocProS (2), 2011)

Alpha-particle-induced effects in partially depleted silicon on insulator device: With and without body contact. - Surendra S. Rathod; Ashok K. Saxena; Sudeb Dasgupta (IET Circuits Devices Syst., 2011)

Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology. - Balwinder Raj; Jatin Mitra; Deepak Kumar Bihani; V. Rangharajan; Ashok K. Saxena; Sudeb Dasgupta (J. Low Power Electron., 2011)

Electrical performance study of 25 nm Omega-FinFET under the influence of gamma radiation: A 3D simulation. - Surendra S. Rathod; Ashok K. Saxena; Sudeb Dasgupta (Microelectron. J., 2011)

Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET. - Santosh Kumar Vishvakarma; V. Komal Kumar; Ashok K. Saxena; Sudeb Dasgupta (Microelectron. J., 2011)

A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier. - Surendra S. Rathod; Ashok K. Saxena; Sudeb Dasgupta (Microelectron. Reliab., 2011)

Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET. - Ashutosh Nandi; Ashok K. Saxena; Sudeb Dasgupta (VDAT, 2012)

Analysis of double-gate FinFET-based address decoder for radiation-induced single-event-transients. - Surendra S. Rathod; Ashok K. Saxena; Sudeb Dasgupta (IET Circuits Devices Syst., 2012)

Dg-FinFET-Based SRAM Configurations for Increased SEU Immunity. - Surendra S. Rathod; Ashok K. Saxena; Sudeb Dasgupta (J. Circuits Syst. Comput., 2012)

Impact of dual-k spacer on analog performance of underlap FinFET. - Ashutosh Nandi; Ashok K. Saxena; Sudeb Dasgupta (Microelectron. J., 2012)

Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET. - Ashutosh Nandi; Ashok K. Saxena; Sudeb Dasgupta (Microelectron. J., 2016)