Novel Formulations for Low-Power Binding of Function Units in High-Level Synthesis. - Ashok Kumar 001; Magdy A. Bayoumi (ICCD, 1999)

Methodologies for binding function units for low power in high level synthesis. - Ashok Kumar 001; Magdy A. Bayoumi (ICECS, 1999)

Multiple voltage-based scheduling methodology for low power in the high level synthesis. - Ashok Kumar 001; Magdy A. Bayoumi (ISCAS (1), 1999)

Minimizing switchings of the function units through binding for low power. - Ashok Kumar 001; Magdy A. Bayoumi; Raghava V. Cherabuddi (ISCAS (1), 1999)

A methodology for low power scheduling with resources operating at multiple voltages. - Ashok Kumar 001; Magdy A. Bayoumi; Mohamed A. Elgamel (Integr., 2004)

An Architecture for Automated Scene Understanding. - Ruth Aguilar-Ponce; Ashok Kumar 001; J. Luis Tecpanecatl-Xihuitl; Magdy A. Bayoumi (CAMP, 2005)

A systematic framework for high throughput MAP decoder VLSI architectures. - Mahmoud Elassal; Ashok Kumar 001; Magdy A. Bayoumi (ISCAS (1), 2005)

A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits. - Walid Elgharbawy; Pradeep Golconda; Ashok Kumar 001; Magdy A. Bayoumi (ISCAS (5), 2005)

Low complexity decimation filter for multi-standard digital receivers. - Ashok Kumar 001; J. Luis Tecpanecatl-Xihuitl; Magdy A. Bayoumi (ISCAS (1), 2005)

Autonomous Decentralized Systems Based Approach to Object Detection in Sensor Clusters. - Ruth Aguilar-Ponce; Ashok Kumar 001; J. Luis Tecpanecatl-Xihuitl; Magdy A. Bayoumi (IEICE Trans. Commun., 2005)

A Fast Scheduling Algorithm for Low Power Design. - Ashok Kumar 001; Magdy A. Bayoumi (J. Circuits Syst. Comput., 2005)

Efficient shield insertion for inductive noise reduction in nanometer technologies. - Mohamed A. Elgamel; Ashok Kumar 001; Magdy A. Bayoumi (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style. - Sumeer Goel; Ashok Kumar 001; Magdy A. Bayoumi (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Intelligent Mechanisms for Energy Reduction in Design of Wireless Sensor Networks using Learning Methods. - Mitun Bhattacharyya; Ashok Kumar 001; Magdy A. Bayoumi (Integrated Intelligent Systems for Engineering Design, 2006)

Pixel-Level Image Fusion Scheme based on Linear Algebra. - Ruth Aguilar-Ponce; J. Luis Tecpanecatl-Xihuitl; Ashok Kumar 001; Magdy A. Bayoumi (ISCAS, 2007)

Design and Realization of Analog Phi-Function for LDPC Decoder. - Abu Baker; Soumik Ghosh; Ashok Kumar 001; Magdy A. Bayoumi; Rafic A. Ayoubi (ISCAS, 2007)

A framework for assessing residual energy in wireless sensor network. - Mitun Bhattacharyya; Ashok Kumar 001; Magdy A. Bayoumi (Int. J. Sens. Networks, 2007)

A network of sensor-based framework for automated visual surveillance. - Ruth Aguilar-Ponce; Ashok Kumar 001; J. Luis Tecpanecatl-Xihuitl; Magdy A. Bayoumi (J. Netw. Comput. Appl., 2007)

Real-time streaming challenges in Internet of Video Things (IoVT). - Ahmed Sammoud; Ashok Kumar 001; Magdy A. Bayoumi; Tarek A. Elarabi (ISCAS, 2017)

An Efficient Approach for Neural Network Architecture. - Kasem Khalil; Omar Eldash; Ashok Kumar 001; Magdy A. Bayoumi (ICECS, 2018)

Flexible Self-Healing Router for Reliable and High-Performance Network-an-Chips Architecture. - Kasem Khalil; Omar Eldash; Ashok Kumar 001; Magdy A. Bayoumi (SoCC, 2018)

Unsupervised Ranking of Numerical Observations based on Magnetic Properties and Correlation Coefficient. - Khalid A. Alattas; Aminul Islam 001; Ashok Kumar 001; Magdy A. Bayoumi (HICSS, 2019)

Demystifying Emerging Nonvolatile Memory Technologies: Understanding Advantages, Challenges, Trends, and Novel Applications. - Rodrigue Rizk; Dominick Rizk; Ashok Kumar 001; Magdy A. Bayoumi (ISCAS, 2019)

A Novel Design Gate based Low-Cost Configurable RO PUF using Reversible Logic. - Bappaditya Dey; Kasem Khalil; Ashok Kumar 001; Magdy A. Bayoumi (MWSCAS, 2019)

Self-Healing Approach for Hardware Neural Network Architecture. - Kasem Khalil; Omar Eldash; Ashok Kumar 001; Magdy A. Bayoumi (MWSCAS, 2019)

A Novel Reconfigurable Hardware Architecture of Neural Network. - Kasem Khalil; Omar Eldash; Bappaditya Dey; Ashok Kumar 001; Magdy A. Bayoumi (MWSCAS, 2019)

N2 OC: Neural-Network-on-Chip Architecture. - Kasem Khalil; Omar Eldash; Ashok Kumar 001; Magdy A. Bayoumi (SoCC, 2019)

A Speed and Energy Focused Framework for Dynamic Hardware Reconfiguration. - Kasem Khalil; Omar Eldash; Ashok Kumar 001; Magdy A. Bayoumi (SoCC, 2019)

Self-healing hardware systems: A review. - Kasem Khalil; Omar Eldash; Ashok Kumar 001; Magdy A. Bayoumi (Microelectron. J., 2019)

Economic LSTM Approach for Recurrent Neural Networks. - Kasem Khalil; Omar Eldash; Ashok Kumar 001; Magdy A. Bayoumi (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Novel Design Reversible Logic Based Configurable Fault-Tolerant Embryonic Hardware. - Kasem Khalil; Bappaditya Dey; Yasser Sherazi; Ashok Kumar 001; Magdy A. Bayoumi (ISCAS, 2020)

A Reversible-Logic based Architecture for Artificial Neural Network. - Bappaditya Dey; Kasem Khalil; Ashok Kumar 001; Magdy A. Bayoumi (MWSCAS, 2020)

Architecture of A Novel Low-Cost Hardware Neural Network. - Kasem Khalil; Omar Eldash; Bappaditya Dey; Ashok Kumar 001; Magdy A. Bayoumi (MWSCAS, 2020)

Dynamically Reconfigurable Deep Learning for Efficient Video Processing in Smart IoT Systems. - Omar Eldash; Adam Frost; Kasem Khalil; Ashok Kumar 001; Magdy A. Bayoumi (WF-IoT, 2020)

Intelligent Fault-Prediction Assisted Self-Healing for Embryonic Hardware. - Kasem Khalil; Omar Eldash; Ashok Kumar 001; Magdy A. Bayoumi (IEEE Trans. Biomed. Circuits Syst., 2020)

Machine Learning-Based Approach for Hardware Faults Prediction. - Kasem Khalil; Omar Eldash; Ashok Kumar 001; Magdy A. Bayoumi (IEEE Trans. Circuits Syst., 2020)

A Reversible-Logic based Architecture for VGGNet. - Bappaditya Dey; Kasem Khalil; Ashok Kumar 001; Magdy A. Bayoumi (ICECS, 2021)

An Efficient Reconfigurable Neural Network on Chip. - Kasem Khalil; Bappaditya Dey; Mostafa Abdelrehim; Ashok Kumar 001; Magdy A. Bayoumi (ICECS, 2021)

A Reversible-Logic Based Architecture for Long Short-Term Memory (LSTM) Network. - Kasem Khalil; Bappaditya Dey; Ashok Kumar 001; Magdy A. Bayoumi (ISCAS, 2021)

A Reversible-Logic based Architecture for Convolutional Neural Network (CNN). - Kasem Khalil; Bappaditya Dey; Ashok Kumar 001; Magdy A. Bayoumi (MWSCAS, 2021)

An Efficient Embryonic Hardware Architecture based on Network-on-Chip. - Kasem Khalil; Omar Eldash; Bappaditya Dey; Ashok Kumar 001; Magdy A. Bayoumi (MWSCAS, 2021)

An In-Situ Sliding Window Approximate Inner-Product Scheme Based on Parallel Distributed Arithmetic for Ultra-Low Power Fault-Tolerant Applications. - Dominick Rizk; Rodrigue Rizk; Frederic Rizk; Ashok Kumar 001 (MWSCAS, 2021)

A Hybrid Capsule Network-based Deep Learning Framework for Deciphering Ancient Scripts with Scarce Annotations: A Case Study on Phoenician Epigraphy. - Rodrigue Rizk; Dominick Rizk; Frederic Rizk; Ashok Kumar 001 (MWSCAS, 2021)

An Efficient Capsule Network Reconfigurable Hardware Accelerator for Deciphering Ancient Scripts with Scarce Annotations. - Rodrigue Rizk; Dominick Rizk; Frederic Rizk; Ashok Kumar 001; Magdy A. Bayoumi (SoCC, 2021)

A Cost-Efficient Reversible-Based Configurable Ring Oscillator Physical Unclonable Function. - Dominick Rizk; Rodrigue Rizk; Frederic Rizk; Ashok Kumar 001; Magdy A. Bayoumi (SoCC, 2021)

Self-Healing Router Approach for High-Performance Network-on-Chip. - Kasem Khalil; Omar Eldash; Ashok Kumar 001; Magdy A. Bayoumi (IEEE Open J. Circuits Syst., 2021)

An Economic Uniqueness-Improved Reliable Reconfigurable RO PUF for IoT Security. - Dominick Rizk; Rodrigue Rizk; Frederic Rizk; Ashok Kumar 001 (ISCAS, 2022)

A Cost-Efficient Reversible-Based Reconfigurable Ring Oscillator Physical Unclonable Function. - Frederic Rizk; Dominick Rizk; Rodrigue Rizk; Ashok Kumar 001 (ISCAS, 2022)

A Resource-Saving Energy-Efficient Reconfigurable Hardware Accelerator for BERT-based Deep Neural Network Language Models using FFT Multiplication. - Rodrigue Rizk; Dominick Rizk; Frederic Rizk; Ashok Kumar 001; Magdy A. Bayoumi (ISCAS, 2022)

Adaptive Hardware Architecture for Neural-Network-on-Chip. - Kasem Khalil; Bappaditya Dey; Ashok Kumar 001; Magdy A. Bayoumi (MWSCAS, 2022)

Reconfigurable Hardware Design Approach for Economic Neural Network. - Kasem Khalil; Ashok Kumar 001; Magdy A. Bayoumi (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Designing Novel AAD Pooling in Hardware for a Convolutional Neural Network Accelerator. - Kasem Khalil; Omar Eldash; Ashok Kumar 001; Magdy A. Bayoumi (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Low-Power Convolutional Neural Network Accelerator on FPGA. - Kasem Khalil; Ashok Kumar 001; Magdy A. Bayoumi (AICAS, 2023)

Efficient Hardware Implementation of Artificial Neural Networks on FPGA. - Kasem Khalil; Tamador Mohaidat; Mahmoud Darwich; Ashok Kumar 001; Magdy A. Bayoumi (AICAS, 2024)

Efficient Deep Learning Approach for Breast Cancer Detection. - Kasem Khalil; Tamador Mohaidat; Mahmoud Darwich; Ashok Kumar 001; Magdy A. Bayoumi (COINS, 2024)

Dynamic Fault Tolerance Approach for Network-on-Chip Architecture. - Kasem Khalil; Ashok Kumar 001; Magdy A. Bayoumi (IEEE J. Emerg. Sel. Topics Circuits Syst., 2024)

Speech Emotion Recognition Using ML Models and Audio Features. - Tytiana James; T. Maheswara Reddy Yenumula; Tanner Mergist; Rafeeq Muhammad; Ali Harimi; Kasem Khalil; Ashok Kumar 001 (SysCon, 2025)

Machine Learning Analysis of Heartbeat Sounds Using Weka for Classification. - Rafeeq Muhammad; T. Maheswara Reddy Yenumula; Tanner Mergist; Tytiana James; Ali Harimi; Kasem Khalil; Ashok Kumar 001 (SysCon, 2025)

An Efficient Neural Cell Architecture for Spiking Neural Networks. - Kasem Khalil; Ashok Kumar 001; Magdy A. Bayoumi (IEEE Open J. Comput. Soc., 2025)

Hardware Acceleration of CoAP Protocol for High-Speed and Low-Power Internet of Things Communication. - Kasem Khalil; Ashok Kumar 001; Magdy A. Bayoumi (IEEE Internet Things J., 2025)

Accurate Hardware Predictor for Epileptic Seizure. - Kasem Khalil; Ashok Kumar 001; Magdy A. Bayoumi (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)