A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks. - Manoj Kumar Goparaju; Ashok Kumar Palaniswamy; Spyros Tragoudas (DFT, 2008)

Scalable identification of threshold logic functions. - Ashok Kumar Palaniswamy; Manoj Kumar Goparaju; Spyros Tragoudas (ACM Great Lakes Symposium on VLSI, 2010)

A scalable threshold logic synthesis method using ZBDDs. - Ashok Kumar Palaniswamy; Spyros Tragoudas (ACM Great Lakes Symposium on VLSI, 2012)

An efficient heuristic to identify threshold logic functions. - Ashok Kumar Palaniswamy; Spyros Tragoudas (ACM J. Emerg. Technol. Comput. Syst., 2012)

ATPG for transition faults of pipelined threshold logic circuits. - Ashok Kumar Palaniswamy; Spyros Tragoudas; Themistoklis Haniotakis (DTIS, 2014)

Improved Threshold Logic Synthesis Using Implicant-Implicit Algorithms. - Ashok Kumar Palaniswamy; Spyros Tragoudas (ACM J. Emerg. Technol. Comput. Syst., 2014)

ATPG for Delay Defects in Current Mode Threshold Logic Circuits. - Ashok Kumar Palaniswamy; Spyros Tragoudas; Themistoklis Haniotakis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)