Leakage aware SER reduction technique for UDSM logic circuits. - Praveen Elakkumanan; Vishwanath Ananthakrishnan; Ashok Narasimhan; Ramalingam Sridhar (SoCC, 2004)

A High-Performance Router Design for VDSM NoCs. - Ashok Narasimhan; Karthik Srinivasan; Ramalingam Sridhar (SoCC, 2005)

A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs. - Ashok Narasimhan; Shantanu Divekar; Praveen Elakkumanan; Ramalingam Sridhar (VLSI Design, 2005)

A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects. - Ashok Narasimhan; Manish Kasotiya; Ramalingam Sridhar (VLSI Design, 2005)

A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects. - Ashok Narasimhan; Bhooma Srinivasaraghavan; Ramalingam Sridhar (VLSI Design, 2006)

Energy Conservation in Sensor Networks through Selective Node Activation. - Prachee Sharma; Asheq Khan; Ashok Narasimhan; Ramalingam Sridhar; Satish K. Tripathi (WOWMOM, 2006)

Impact of Variability on Clock Skew in H-tree Clock Networks. - Ashok Narasimhan; Ramalingam Sridhar (ISQED, 2007)

A low power and low area active clock deskewing technique for sub-90nm technologies. - Ashok Narasimhan; Ramalingam Sridhar (SoCC, 2008)

Variation aware low power buffered interconnect design. - Ashok Narasimhan; Ramalingam Sridhar (SoCC, 2009)

Variability Aware Low-Power Delay Optimal Buffer Insertion for Global Interconnects. - Ashok Narasimhan; Ramalingam Sridhar (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)