Improved time series segmentation using gated experts with simulated annealing. - Ashok Srivastava; Andreas Wieigend (ICNN, 1996)

Influence of BJT Transit Frequency Limit Relation to MOSFET Parameters on the Switching Speed of BiCMOS Digital Circuits. - Ashok Srivastava (VLSI Design, 1999)

Quaternary to binary bit conversion CMOS integrated circuit design using multiple-input floating gate MOSFETS. - Ashok Srivastava; Harish N. Venkata (Integr., 2003)

Phase noise analysis for ICI self-cancellation coded OFDM with short-channel synchronization devices. - Sameer R. Herlekar; Hsiao-Chun Wu; Chi Zhang; Ashok Srivastava (GLOBECOM, 2005)

Sensitivity of single-carrier QAM systems to phase noise arising from the hot-carrier effect. - Sameer R. Herlekar; Hsiao-Chun Wu; Ashok Srivastava (WCNC, 2006)

OFDM performance analysis in the phase noise arising from the hot-carrier effect. - Sameer R. Herlekar; Chi Zhang; Hsiao-Chun Wu; Ashok Srivastava; Yiyan Wu 001 (IEEE Trans. Consumer Electron., 2006)

Hot Carrier Effects in Wireless Communication Systems Built on Short-Channel MOSFETs. - Hsiao-Chun Wu; Sameer R. Herlekar; M. Saquib; Ashok Srivastava (IEEE Trans. Wirel. Commun., 2007)

Stable and Efficient Gaussian Process Calculations. - Leslie Foster; Alex Waagen; Nabeela Aijaz; Michael Hurley; Apolonio Luis; Joel Rinsky; Chandrika Satyavolu; Michael J. Way; Paul R. Gazis; Ashok Srivastava (J. Mach. Learn. Res., 2009)

Hot carrier effects on CMOS phase-locked loop frequency synthesizers. - Yang Liu; Ashok Srivastava (ISQED, 2010)

A model for carbon nanotube interconnects. - Yao Xu; Ashok Srivastava (Int. J. Circuit Theory Appl., 2010)

Switchable PLL Frequency Synthesizer and Hot Carrier Effects. - Yang Liu; Ashok Srivastava; Yao Xu (Circuits Syst., 2011)

ΔIDDQ Testing of a CMOS Digital-to-Analog Converter Considering Process Variation Effects. - Rajiv Soundararajan; Ashok Srivastava; Siva Sankar Yellampalli (Circuits Syst., 2011)

Testing of Trusted CMOS Data Converters. - Ashok Srivastava; Rajiv Soundararajan (ISVLSI, 2012)

Analysis of Virtual Sensors for Predicting Aircraft Fuel Consumption. - Timothy Woodbury; Ashok Srivastava (Infotech@Aerospace, 2012)

Top-10 Data Mining Case Studies. - Gabor Melli; Xindong Wu 001; Paul Beinat; Francesco Bonchi; Longbing Cao; Rong Duan; Christos Faloutsos; Rayid Ghani; Brendan Kitts; Bart Goethals; Geoffrey J. McLachlan; Jian Pei 001; et al. (Int. J. Inf. Technol. Decis. Mak., 2012)

CMOS LC voltage controlled oscillator design using multiwalled and single-walled carbon nanotube wire inductors. - Ashok Srivastava; Yao Xu; Yang Liu; Ashwani K. Sharma; Clay Mayberry (ACM J. Emerg. Technol. Comput. Syst., 2012)

CMOS Phase-Locked Loop Circuits and Hot Carrier Effects. - Yang Liu; Ashok Srivastava (J. Low Power Electron., 2012)

A Programmable Oversampling CMOS Delta-Sigma Analog-to-Digital Converter for Low-Power Interface Electronics. - Rajiv Soundararajan; Ashok Srivastava (J. Low Power Electron., 2012)

A novel graphene nanoribbon field effect transistor for integrated circuit design. - Yaser Mohammadi Banadaki; Ashok Srivastava (MWSCAS, 2013)

Classification and Adaptive Novel Class Detection of Feature-Evolving Data Streams. - Mohammad M. Masud 001; Qing Chen; Latifur Khan; Charu C. Aggarwal; Jing Gao 004; Jiawei Han 001; Ashok Srivastava; Nikunj C. Oza (IEEE Trans. Knowl. Data Eng., 2013)

Increasing off-chip bandwidth in multi-core processors with switchable pins. - Shaoming Chen; Yue Hu; Ying Zhang 016; Lu Peng 001; Jesse Ardonne; Samuel Irving; Ashok Srivastava (ISCA, 2014)

Characterization of MWCNT VLSI Interconnect with Self-Heating Induced Scatterings. - K. M. Mohsin; Ashok Srivastava; Ashwani K. Sharma; Clay Mayberry (ISVLSI, 2014)

Low Power-Variable Resolution Analog-to-Digital Converter. - Saloni Varshney; Manish Goswami; B. R. Singh; Ashok Srivastava (J. Low Power Electron., 2014)

Characterization of SWCNT Bundle Based VLSI Interconnect with Self-heating Induced Scatterings. - K. M. Mohsin; Ashok Srivastava (ACM Great Lakes Symposium on VLSI, 2015)

Clocked Adiabatic XOR and XNOR CMOS Gates Design Based on Graphene Nanoribbon Complementary Field Effect Transistors. - Yaser Mohammadi Banadaki; Ashok Srivastava; Safura Sharifi (iNIS, 2015)

Circuit Implementation of Switchable Pins in Chip Multiprocessor. - Zhou Zhao; Ashok Srivastava; Lu Peng 001; Shaoming Chen; Saraju P. Mohanty (iNIS, 2015)

An Algorithm Used in a Power Monitor to Mitigate Dark Silicon on VLSI Chip. - Zhou Zhao; Ashok Srivastava; Shaoming Chen; Saraju P. Mohanty (ISVLSI, 2015)

Scaling Effects on Static Metrics and Switching Attributes of Graphene Nanoribbon FET for Emerging Technology. - Yaser Mohammadi Banadaki; Ashok Srivastava (IEEE Trans. Emerg. Top. Comput., 2015)

Powering Up Dark Silicon: Mitigating the Limitation of Power Delivery via Dynamic Pin Switching. - Shaoming Chen; Lu Peng 001; Yue Hu; Zhou Zhao; Ashok Srivastava; Ying Zhang 016; Jin-Woo Choi; Bin Li 008; Edward Song (IEEE Trans. Emerg. Top. Comput., 2015)

Width-Dependent Characteristics of Graphene Nanoribbon Field Effect Transistor for High Frequency Applications. - Yaser Mohammadi Banadaki; Ashok Srivastava (iNIS, 2016)

Modeling of Graphene Nanoribbon Tunnel Field Effect Transistor in Verilog-A for Digital Circuit Design. - Md. Fahad; Zhou Zhao; Ashok Srivastava; Lu Peng 001 (iNIS, 2016)

A Low-Cost Mixed Clock Generator for High Speed Adiabatic Logic. - Zhou Zhao; Ashok Srivastava; Lu Peng 001; Saraju P. Mohanty (ISVLSI, 2016)

Large-Scale Machine Learning at Verizon: Theory and Applications. - Ashok Srivastava (KDD, 2016)

Compact Modeling of Graphene Barristor for Digital Integrated Circuit Design. - Zhou Zhao; Xinlu Chen; Ashok Srivastava; Lu Peng 001; Saraju P. Mohanty (ISVLSI, 2017)

Foreword to the Applied Data Science: Invited Talks Track at KDD-2017. - Usama M. Fayyad; Evangelos Simoudis; Ashok Srivastava (KDD, 2017)

Guest editorial - Special issue on hardware assisted techniques for IoT and bigdata applications. - Saraju P. Mohanty; Ashok Srivastava; Shiyan Hu 001; Prasun Ghosal (Integr., 2017)

A novel switchable pin method for regulating power in chip-multiprocessor. - Zhou Zhao; Ashok Srivastava; Lu Peng 001; Shaoming Chen; Saraju P. Mohanty (Integr., 2017)

Using Switchable Pins to Increase Off-Chip Bandwidth in Chip-Multiprocessors. - Shaoming Chen; Samuel Irving; Lu Peng 001; Yue Hu; Ying Zhang 016; Ashok Srivastava (IEEE Trans. Parallel Distributed Syst., 2017)

Modeling of Joule Heating Induced Effects in Multiwall Carbon Nanotube Interconnects. - K. M. Mohsin; Ashok Srivastava (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Evaluation of Four Power Gating Schemes Applied to ECRL Adiabatic Logic. - William Morell; Ashok Srivastava (MWSCAS, 2018)

Improving robustness of classifiers by training against live traffic. - Kumar Sricharan; Kumar Kallurupalli; Ashok Srivastava (CoRR, 2018)

Building robust classifiers through generation of confident out of distribution examples. - Kumar Sricharan; Ashok Srivastava (CoRR, 2018)

Calibration method to reduce the error in logarithmic conversion with its circuit implementation. - Zhou Zhao; Ashok Srivastava; Lu Peng 001; Saraju P. Mohanty (IET Circuits Devices Syst., 2018)

A Multiple Input Floating Gate Based Arithmetic Logic Unit with a Feedback Loop for Digital Calibration. - Zhou Zhao; Ashok Srivastava; Lu Peng 001; Saraju P. Mohanty (J. Low Power Electron., 2018)

qSwitch: Dynamical Off-Chip Bandwidth Allocation Between Local and Remote Accesses. - Shaoming Chen; Lu Peng 001; Samuel Irving; Zhou Zhao; Weihua Zhang; Ashok Srivastava (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

AI for Small Businesses and Consumers: Applications and Innovations. - Ashok Srivastava (KDD, 2019)

Novel, Low-power ECRL-CMOS Interface Circuit. - William Morell; Ashok Srivastava (MWSCAS, 2019)

Long Short-Term Memory Network Design for Analog Computing. - Zhou Zhao; Ashok Srivastava; Lu Peng 001; Qing Chen (ACM J. Emerg. Technol. Comput. Syst., 2019)

A 250 MHz-to-1.6 GHz Phase Locked Loop Design in Hybrid FinFET-Memristor Technology. - Naheem Olakunle Adesina; Ashok Srivastava (UEMCON, 2020)

0.4 mW, 0.27 pJ/bit true random number generator using jitter, metastability and current starved topology. - Dhirendra Kumar; Rahul Anand; Sajai Vir Singh; Prasanna Kumar Misra; Ashok Srivastava; Manish Goswami (IET Circuits Devices Syst., 2020)

High Q-Factor Graphene-Based Inductor CMOS LC Voltage Controlled Oscillator for PLL Applications. - Naheem Olakunle Adesina; Md Azmot Ullah Khan; Ashok Srivastava (CCECE, 2021)

Evaluating the Performances of Memristor, FinFET, and Graphene TFET in VLSI Circuit Design. - Naheem Olakunle Adesina; Ashok Srivastava; Md Azmot Ullah Khan (CCWC, 2021)