Minimal Delay Interconnect Design Using Alphabetic Trees. - Ashok Vittal; Malgorzata Marek-Sadowska (DAC, 1994)

Power Optimal Buffered Clock Tree Design. - Ashok Vittal; Malgorzata Marek-Sadowska (DAC, 1995)

Power Distribution Topology Design. - Ashok Vittal; Malgorzata Marek-Sadowska (DAC, 1995)

Clock skew optimization for ground bounce control. - Ashok Vittal; Hein Ha; Forrest Brewer; Malgorzata Marek-Sadowska (ICCAD, 1996)

Crosstalk reduction for VLSI. - Ashok Vittal; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Low-power buffered clock tree design. - Ashok Vittal; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Power Distribution Synthesis for VLSI. - Ashok Vittal; Malgorzata Marek-Sadowska (VLSI Design, 1998)

Modeling Crosstalk in Resistive VLSI Interconnections. - Ashok Vittal; Lauren Hui Chen; Malgorzata Marek-Sadowska; Kai-Ping Wang; Sherry Yang 003 (VLSI Design, 1999)

Crosstalk in VLSI interconnections. - Ashok Vittal; Lauren Hui Chen; Malgorzata Marek-Sadowska; Kai-Ping Wang; Sherry Yang 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)