Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits. - Ashutosh Chakraborty; Karthik Duraisami; Ashoka Visweswara Sathanur; Prassanna Sithambaram; Alberto Macii; Enrico Macii; Massimo Poncino (ISCAS, 2006)

Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. - Ashutosh Chakraborty; Karthik Duraisami; Ashoka Visweswara Sathanur; Prassanna Sithambaram; Alberto Macii; Enrico Macii; Massimo Poncino (PATMOS, 2006)

Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. - Ashoka Visweswara Sathanur; Andrea Calimera; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (DATE, 2007)

Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. - Andrea Calimera; Antonio Pullini; Ashoka Visweswara Sathanur; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2007)

Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew. - Karthik Duraisami; Prassanna Sithambaram; Ashoka Visweswara Sathanur; Alberto Macii; Enrico Macii; Massimo Poncino (ISCAS, 2007)

Timing-driven row-based power gating. - Ashoka Visweswara Sathanur; Antonio Pullini; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (ISLPED, 2007)

A Scalable Algorithmic Framework for Row-Based Power-Gating. - Ashoka Visweswara Sathanur; Antonio Pullini; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (DATE, 2008)

Optimal sleep transistor synthesis under timing and area constraints. - Ashoka Visweswara Sathanur; Antonio Pullini; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2008)

On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. - Ashoka Visweswara Sathanur; Andrea Calimera; Antonio Pullini; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (ISCAS, 2008)

Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction. - Ashoka Visweswara Sathanur; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (ISLPED, 2008)

Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating. - Ashoka Visweswara Sathanur; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (PATMOS, 2008)

Implementation of a thermal management unit for canceling temperature-dependent clock skew variations. - Ashutosh Chakraborty; Karthik Duraisami; Ashoka Visweswara Sathanur; Prassanna Sithambaram; Alberto Macii; Enrico Macii; Massimo Poncino (Integr., 2008)

Thermal-Aware Design Techniques for Nanometer CMOS Circuits. - Andrea Calimera; Karthik Duraisami; Ashoka Visweswara Sathanur; Prassanna Sithambaram; R. Iris Bahar; Alberto Macii; Enrico Macii; Massimo Poncino (J. Low Power Electron., 2008)

Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers. - Ashutosh Chakraborty; Karthik Duraisami; Ashoka Visweswara Sathanur; Prassanna Sithambaram; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Physically clustered forward body biasing for variability compensation in nanometer CMOS design. - Ashoka Visweswara Sathanur; Antonio Pullini; Luca Benini; Giovanni De Micheli; Enrico Macii (DATE, 2009)

Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating. - Ashoka Visweswara Sathanur; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (J. Low Power Electron., 2009)

Activity profile driven simultaneous vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designs. - Ashoka Visweswara Sathanur; Jos Huisken; Jan Stuyt; Harmke de Groot (ICECS, 2010)

Automatic synthesis of near-threshold circuits with fine-grained performance tunability. - Mohammad Reza Kakoee; Ashoka Visweswara Sathanur; Antonio Pullini; Jos Huisken; Luca Benini (ISLPED, 2010)

Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications. - Antonio Artés; José Luis Ayala; Ashoka Visweswara Sathanur; Jos Huisken; Francky Catthoor (VLSI-SoC, 2011)

Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating. - Ashoka Visweswara Sathanur; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits. - Ashoka Visweswara Sathanur; Luca Benini; Alberto Macii; Enrico Macii; Massimo Poncino (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Row-based FBB: A design-time optimization for post-silicon tunable circuits. - Mohammad Reza Kakoee; Ashoka Visweswara Sathanur; Antonio Pullini; Luca Benini (Microelectron. J., 2012)