8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3rd order, 3/5-bit IIR and 3rd order 3-bit-FIR noise shapers in 90nm CMOS. - Ashoke Ravi; Ralph E. Bishop; L. Richard Carley; Krishnamurthy Soumyanath (CICC, 2004)

A 90-nm MOS-only 3-11GHz transmitter for UWB. - Yorgos Palaskas; Ralph E. Bishop; Ashoke Ravi; Krishnamurthy Soumyanath (CICC, 2005)

A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correction. - Yorgos Palaskas; Stewart S. Taylor; Stefano Pellerano; Ian A. Rippke; Ralph E. Bishop; Ashoke Ravi; Hasnain Lakdawala; Krishnamurthy Soumyanath (CICC, 2005)

A 9-b 400 Msample/s pipelined analog-to digital converter in 90nm CMOS. - Charles T. Peach; Ashoke Ravi; Rosie Bishop; Krishnamurthy Soumyanath; David J. Allstot (ESSCIRC, 2005)

A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS. - Sunghyun Park 006; Yorgos Palaskas; Ashoke Ravi; Ralph E. Bishop; Michael P. Flynn (CICC, 2006)

A 5GHz 108Mb/s 2x2 MIMO Transceiver with Fully Integrated +16dBm PAs in 90nm CMOS. - Yorgos Palaskas; Ashoke Ravi; Stefano Pellerano; Brent R. Carlton; Mostafa A. Elmala; Ralph E. Bishop; Gaurab Banerjee; Rich B. Nicholls; Stanley K. Ling; Stewart S. Taylor; Krishnamurthy Soumyanath (ISSCC, 2006)

A 5-GHz 108-Mb/s 2 $ times$2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm ${ rm P}_{ rm 1dB}$ Power Amplifiers in 90-nm CMOS. - Yorgos Palaskas; Ashoke Ravi; Stefano Pellerano; Brent R. Carlton; Mostafa A. Elmala; Ralph E. Bishop; Gaurab Banerjee; Rich B. Nicholls; Stanley K. Ling; Nati Dinur; Stewart S. Taylor; Krishnamurthy Soumyanath (IEEE J. Solid State Circuits, 2006)

A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process. - Yorgos Palaskas; Stewart S. Taylor; Stefano Pellerano; Ian A. Rippke; Ralph E. Bishop; Ashoke Ravi; Hasnain Lakdawala; Krishnamurthy Soumyanath (IEEE J. Solid State Circuits, 2006)

MIMO techniques for high data rate radio communications. - Yorgos Palaskas; Ashoke Ravi; Stefano Pellerano (CICC, 2008)

A 1.7-GHz 1.5-mW digitally-controlled FBAR oscillator with 0.03-ppb resolution. - Hiroyuki Ito; Hasnain Lakdawala; Ashoke Ravi; Stefano Pellerano; Rick Ruby; Krishnamurthy Soumyanath; Kazuya Masu (ESSCIRC, 2008)

A 3.6GHz, 16mW ΣΔ DAC for a 802.11n / 802.16e transmitter with 30dB digital power control in 90nm CMOS. - Parmoon Seddighrad; Ashoke Ravi; Masoud Sajadieh; Hasnain Lakdawala; Krishnamurthy Soumyanath (ESSCIRC, 2008)

A 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS. - Stefano Pellerano; Rajarshi Mukhopadhyay; Ashoke Ravi; Joy Laskar; Yorgos Palaskas (ISSCC, 2008)

A 28.6dBm 65nm Class-E PA with Envelope Restoration by Pulse-Width and Pulse-Position Modulation. - Jeffrey S. Walling; Hasnain Lakdawala; Yorgos Palaskas; Ashoke Ravi; Ofir Degani; Krishnamurthy Soumyanath; David J. Allstot (ISSCC, 2008)

A 2.5GHz, 6.9mW ΔΣ modulator with standard cell design in 45nm-LP CMOS using time-interleaving. - Paolo Madoglio; Ashoke Ravi; Luis Cuellar 001; Stefano Pellerano; Parmoon Seddighrad; Ismael Lomeli; Yorgos Palaskas (ESSCIRC, 2009)

A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS. - Jeffrey S. Walling; Hasnain Lakdawala; Yorgos Palaskas; Ashoke Ravi; Ofir Degani; Krishnamurthy Soumyanath; David J. Allstot (IEEE J. Solid State Circuits, 2009)

A highly linear 25dBm outphasing power amplifier in 32nm CMOS for WLAN application. - Hongtao Xu; Yorgos Palaskas; Ashoke Ravi; Krishnamurthy Soumyanath (ESSCIRC, 2010)

A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving. - Paolo Madoglio; Ashoke Ravi; Luis Cuellar 001; Stefano Pellerano; Parmoon Seddighrad; Ismael Lomeli; Yorgos Palaskas (IEEE J. Solid State Circuits, 2010)

A 31.5dBm outphasing class-D power amplifier in 45nm CMOS with back-off efficiency enhancement by dynamic power control. - Wei Tai; Hongtao Xu; Ashoke Ravi; Hasnain Lakdawala; Ofir B. Degani; L. Richard Carley; Yorgos Palaskas (ESSCIRC, 2011)

A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application. - Hongtao Xu; Yorgos Palaskas; Ashoke Ravi; Masoud Sajadieh; Mohammed A. El-Tanani; Krishnamurthy Soumyanath (IEEE J. Solid State Circuits, 2011)

A digital fractional-N PLL with a 3mW 0.004mm2 6-bit PVT and mismatch insensitive TDC. - Hyung Seok Kim; Carlos Ornelas; Kailash Chandrashekar; Pin-en Su; Paolo Madoglio; Yee William Li; Ashoke Ravi (ESSCIRC, 2012)

A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management. - Kailash Chandrashekar; Stefano Pellerano; Paolo Madoglio; Ashoke Ravi; Yorgos Palaskas (ISSCC, 2012)

A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS. - Y. William Li; Carlos Ornelas; Hyung Seok Kim; Hasnain Lakdawala; Ashoke Ravi; Krishnamurthy Soumyanath (ISSCC, 2012)

A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS. - Paolo Madoglio; Ashoke Ravi; Hongtao Xu; Kailash Chandrashekar; Marian Verhelst; Stefano Pellerano; Luis Cuellar 001; Mariano Aguirre; Masoud Sajadieh; Ofir B. Degani; Hasnain Lakdawala; Yorgos Palaskas (ISSCC, 2012)

A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS. - Yulin Tan; Jon Duster; Chang-Tsung Fu; Erkan Alpman; Ajay Balankutty; Chun C. Lee; Ashoke Ravi; Stefano Pellerano; Kailash Chandrashekar; Hyung Seok Kim; Brent R. Carlton; Satoshi Suzuki; et al. (VLSIC, 2012)

A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS. - Ashoke Ravi; Paolo Madoglio; Hongtao Xu; Kailash Chandrashekar; Marian Verhelst; Stefano Pellerano; Luis Cuellar 001; Mariano Aguirre-Hernandez; Masoud Sajadieh; J. E. Zarate-Roldan; Ofir Bochobza-Degani; Hasnain Lakdawala; et al. (IEEE J. Solid State Circuits, 2012)

A Transformer-Combined 31.5 dBm Outphasing Power Amplifier in 45 nm LP CMOS With Dynamic Power Control for Back-Off Power Efficiency Enhancement. - Wei Tai; Hongtao Xu; Ashoke Ravi; Hasnain Lakdawala; Ofir B. Degani; L. Richard Carley; Yorgos Palaskas (IEEE J. Solid State Circuits, 2012)

A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique. - Hyung Seok Kim; Carlos Ornelas; Kailash Chandrashekar; Dan Shi; Pin-en Su; Paolo Madoglio; Yee William Li; Ashoke Ravi (IEEE J. Solid State Circuits, 2013)

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver. - Hasnain Lakdawala; Mark Schaecher; Chang-Tsung Fu; Rahul Dilip Limaye; Jon Duster; Yulin Tan; Ajay Balankutty; Erkan Alpman; Chun C. Lee; Khoa Minh Nguyen; Hyung-Jin Lee; Ashoke Ravi; et al. (IEEE J. Solid State Circuits, 2013)

Wi-Fi RF energy harvesting for battery-free wearable radio platforms. - Vamsi Talla; Stefano Pellerano; Hongtao Xu; Ashoke Ravi; Yorgos Palaskas (IEEE RFID, 2015)

2.9 A 2GHz 244fs-resolution 1.2ps-Peak-INL edge-interpolator-based digital-to-time converter in 28nm CMOS. - Sebastian Sievert; Ofir B. Degani; Assaf Ben Bassat; Rotem Banin; Ashoke Ravi; Bernd-Ulrich Klepser; Zdravko Boos; Doris Schmitt-Landsiedel (ISSCC, 2016)

A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS. - Sebastian Sievert; Ofir Degani; Assaf Ben Bassat; Rotem Banin; Ashoke Ravi; Wolfgang Thomann; Bernd-Ulrich Klepser; Zdravko Boos; Doris Schmitt-Landsiedel (IEEE J. Solid State Circuits, 2016)

A 32nm, 0.65-10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O. - William Y. Li; Hyung Seok Kim; Kailash Chandrashekar; Khoa Minh Nguyen; Ashoke Ravi (ISLPED, 2017)

13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications. - Paolo Madoglio; Hongtao Xu; Kailash Chandrashekar; Luis Cuellar 001; Muhammad Faisal; Yee William Li; Hyung Seok Kim; Khoa Minh Nguyen; Yulin Tan; Brent R. Carlton; Vaibhav A. Vaidya; Yanjie Wang; et al. (ISSCC, 2017)

A Dual-Mode Configurable RF-to-Digital Receiver in 16NM FinFET. - Amy Whitcombe; Borivoje Nikolic; Farhana Sheikh; Erkan Alpman; Ashoke Ravi (VLSI Circuits, 2018)

802.11g/n Compliant Fully Integrated Wake-Up Receiver With -72-dBm Sensitivity in 14-nm FinFET CMOS. - Erkan Alpman; Ahmad Khairi; Richard Dorrance; Minyoung Park; V. Srinivasa Somayazulu; Jeffrey R. Foerster; Ashoke Ravi; Jeyanandh Paramesh; Stefano Pellerano (IEEE J. Solid State Circuits, 2018)

A Cellular Multiband DTC-Based Digital Polar Transmitter With -153 dBc/Hz Noise in 14-nm FinFET. - Yorgos Palaskas; Peter Plechinger; Ashoke Ravi; Ofir Degani; Rotem Banin; Eshel Gordon; Zdravko Boos; Paolo Madoglio; Jörn Angel; Jakob M. Tomasik; Sven Hampel; Petra Schubert; et al. (ESSCIRC, 2019)

10.5 A Fully Integrated 27dBm Dual-Band All-Digital Polar Transmitter Supporting 160MHz for WiFi 6 Applications. - Assaf Ben Bassat; Shahar Gross; Anna Nazimov; Ashoke Ravi; Bassam Khamaisi; Elan Banin; Eli Borokhovich; Nahum Kimiagarov; Phillip Skliar; Rotem Banin; Sarit Zur; Sebastian Reinhold; et al. (ISSCC, 2020)

A Fully Integrated 27-dBm Dual-Band All-Digital Polar Transmitter Supporting 160 MHz for Wi-Fi 6 Applications. - Assaf Ben Bassat; Shahar Gross; Aaron Lane; Anna Nazimov; Bassam Khamaisi; Elad Solomon; Elan Banin; Eli Borokhovich; Nahum Kimiagorov; Nati Dinur; Phillip Skliar; Roi Cohen; et al. (IEEE J. Solid State Circuits, 2020)

A Cellular Multiband DTC-Based Digital Polar Transmitter With -153-dBc/Hz Noise in 14-nm FinFET. - Paolo Madoglio; Yorgos Palaskas; Jörn Angel; Jakob M. Tomasik; Sven Hampel; Petra Schubert; Peter Preyler; Thomas Mayer 003; Thomas Bauernfeind; Peter Plechinger; Ashoke Ravi; Ofir Degani; et al. (IEEE J. Solid State Circuits, 2020)

A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS. - Edwin Thaller; Run Levinger; Evgeny Shumaker; Aryeh Farber; Sergey Bershansky; Nir Geron; Ashoke Ravi; Rotem Banin; Jasmin Kadry; Gil Horovitz; Christian Krassnitzer; Christoph Duller; et al. (ISSCC, 2021)

A 16nm, +28dBm Dual-Band All-Digital Polar Transmitter Based on 4-core Digital PA for Wi-Fi6E Applications. - Bassam Khamaisi; David Ben-Haim; Anna Nazimov; Assaf Ben Bassat; Shahar Gross; N. Shay; G. Asa; V. Spector; Yishai Eilat; A. Azam; Eli Borokhovich; I. Shternberg; et al. (ISSCC, 2022)

A 1.8W High-Frequency SIMO Converter Featuring Digital Sensor-Less Computational Zero-Current Operation and Non-Linear Duty-Boost. - Suhwan Kim 002; Harish K. Krishnamurthy; Sergey Sofer; Sheldon Weng; Shahar Wolf; Ashoke Ravi; Krishnan Ravichandran; Ofir Degani; James W. Tschanz; Vivek De (ISSCC, 2023)