Design and Analysis of Sub-DT Sub-Domino Logic Circuits for Ultra Low Power Applications. - Ashutosh Nandi; Rajeevan Chandel (J. Low Power Electron., 2010)

Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET. - Ashutosh Nandi; Ashok K. Saxena; Sudeb Dasgupta (VDAT, 2012)

Impact of dual-k spacer on analog performance of underlap FinFET. - Ashutosh Nandi; Ashok K. Saxena; Sudeb Dasgupta (Microelectron. J., 2012)

Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET. - Ashutosh Nandi; Ashok K. Saxena; Sudeb Dasgupta (Microelectron. J., 2016)

Comparative study of 16-order FIR filter design using different multiplication techniques. - Anubhuti Mittal; Ashutosh Nandi; Disha Yadav (IET Circuits Devices Syst., 2017)

Effect of air spacer in underlap GAA nanowire: an analogue/RF perspective. - Shikhar Gupta; Ashutosh Nandi (IET Circuits Devices Syst., 2019)

Temperature analysis of underlap GAA-SNWTs for analog/RF applications. - Shikhar Gupta; Ashutosh Nandi (Microelectron. J., 2019)