Programmable Binary Weighted Time-Domain Vector Matrix Multiplier for In-Memory Computing. - Bipul Boro; Ashvinikumar Dongre; Rushik Parmar; Gaurav Trivedi (APCCAS, 2023)

Binary Synaptic Array for Inference and Training with Built-in RRAM Electroforming Circuit. - Ashvinikumar Dongre; Gaurav Trivedi (ISQED, 2023)

RRAM-Based Energy Efficient Scalable Integrate and Fire Neuron With Built-In Reset Circuit. - Ashvinikumar Dongre; Gaurav Trivedi (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

ADC-Less Reprogrammable RRAM Array Architecture for In-Memory Computing. - Ashvinikumar Dongre; Bipul Boro; Gaurav Trivedi (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Reprogrammable Time-Domain RRAM Based Vector Matrix Multiplier for In-Memory Computing. - Bipul Boro; Rushik Parmar; Ashvinikumar Dongre; Gaurav Trivedi (ISQED, 2024)