Performance evaluation of FD-SOI Mosfets for different metal gate work function - Deepesh Ranka; Ashwani K. Rana; Rakesh Kumar Yadav; Kamalesh Yadav; Devendra Giri (CoRR, 2011)

Modeling gate Current for nano Scale MOSFET with Different gate spacer. - Ashwani K. Rana; Narottam Chand; Vinod Kapoor (J. Circuits Syst. Comput., 2011)

DA-Based Efficient Testable FIR Filter Implementation on FPGA Using Reversible Logic. - Amita Nandal; T. Vigneswaran; Ashwani K. Rana (Circuits Syst. Signal Process., 2014)

Strained Si: Opportunities and challenges in nanoscale MOSFET. - Rajneesh Sharma; Ashwani K. Rana (ReTIS, 2015)

Impact of Work Function Fluctuations on Threshold Voltage Variability in a Nanoscale FinFETs. - Rituraj Singh Rathore; Rajneesh Sharma; Ashwani K. Rana (iNIS, 2016)

Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET. - Rajneesh Sharma; Rituraj S. Rathore; Ashwani K. Rana (J. Circuits Syst. Comput., 2018)

Evaluation of statistical variability and parametric sensitivity of non-uniformly doped Junctionless FinFET. - Shalu Kaundal; Ashwani K. Rana (Microelectron. Reliab., 2018)

Analytical model of subthreshold drain current for nanoscale negative capacitance junctionless FinFET. - Shelja Kaushal; Ashwani K. Rana (Microelectron. J., 2022)

Reliable and low power Negative Capacitance Junctionless FinFET based 6T SRAM cell. - Shelja Kaushal; Ashwani K. Rana (Integr., 2023)