A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays. - Ashwin Chintaluri; Abhinav Parihar; Suriyaprakash Natarajan; Helia Naeimi; Arijit Raychowdhury (ATS, 2015)

EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays. - Insik Yoon; Ashwin Chintaluri; Arijit Raychowdhury (ITC, 2016)

Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays. - Ashwin Chintaluri; Helia Naeimi; Suriyaprakash Natarajan; Arijit Raychowdhury (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links. - Mahmut Yilmaz; Pavan Kumar Datla Jagannadha; Kaushik Narayanun; Shantanu Sarangi; Francisco Da Silva; Joe Sarmiento; Smbat Tonoyan; Ashwin Chintaluri; Animesh Khare; Milind Sonawane; Ashish Kumar; Anitha Kalva; et al. (VTS, 2022)