Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture. - Avinash Karanth Kodi; Ashwini Sarathy; Ahmed Louri (ANCS, 2007)

iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures. - Avinash Karanth Kodi; Ashwini Sarathy; Ahmed Louri (ISCA, 2008)

Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis. - Avinash Karanth Kodi; Ashwini Sarathy; Ahmed Louri (IEEE Trans. Computers, 2008)

Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures. - Avinash Karanth Kodi; Ashwini Sarathy; Ahmed Louri; Janet Meiling Wang (ASP-DAC, 2009)

Co-design of channel buffers and crossbar organizations in NoCs architectures. - Avinash Karanth Kodi; Randy Morris; Dominic DiTomaso; Ashwini Sarathy; Ahmed Louri (ICCAD, 2011)

Design of a Concentrated Torus Topology with Channel Buffers and Efficient Crossbars in NoCs. - Dominic DiTomaso; Randy Morris; Evan Jolley; Ashwini Sarathy; Ahmed Louri; Avinash Karanth Kodi (IPDPS Workshops, 2013)

Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips. - Dominic DiTomaso; Randy Morris; Avinash Karanth Kodi; Ashwini Sarathy; Ahmed Louri (IEEE Trans. Very Large Scale Integr. Syst., 2013)