An On-Line Optimization Procedure for an Urban Traffic System. - C. J. Macleod; Asim J. Al-Khalili (Optimization Techniques, 1973)

An Algorithm for an Intelligent Arabic Computer Terminal. - Asim J. Al-Khalili (Int. J. Man Mach. Stud., 1984)

Urban traffic control - A general approach. - Asim J. Al-Khalili (IEEE Trans. Syst. Man Cybern., 1985)

A general approach to relative offset settings of traffic signals. - Asim J. Al-Khalili (IEEE Trans. Syst. Man Cybern., 1985)

The optimum green split of a cycle time. - Asim J. Al-Khalili (IEEE Trans. Syst. Man Cybern., 1985)

A micro-manipulator vision in IC Manufacturing. - Ram Dantu; Nikitas J. Dimopoulos; Rajni V. Patel; Asim J. Al-Khalili (ICRA, 1988)

An algorithm for polygon conversion to boxes for VLSI layouts. - Asim J. Al-Khalili; Dhamin Al-Khalili; K. Ammar (Integr., 1988)

Design of optimal systolic arrays: a systematic approach. - Michael Ogbonna Esonu; Asim J. Al-Khalili; Salim Hariri (SPDP, 1990)

A module generator for optimized CMOS buffers. - Asim J. Al-Khalili; Yong Zhu; Dhamin Al-Khalili (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

Area Efficient Computing Structures for Concurrent Error Detection in Systolic Architectures. - Michael Ogbonna Esonu; Asim J. Al-Khalili; Salim Hariri (ICPP (1), 1991)

On the Design of Optimal Fault-Tolerant Systolic Array Architecures. - Michael Ogbonna Esonu; Asim J. Al-Khalili; Salim Hariri (IPPS, 1991)

Depth perception using blurring and its application in VLSI wafer probing. - R. V. Dantu; Nikitas J. Dimopoulos; Rajni V. Patel; A. J. Al-Khalili (Mach. Vis. Appl., 1991)

Power estimation tool for sub-micron CMOS VLSI circuits. - F. Rouatbi; Baher Haroun; Asim J. Al-Khalili (ICCAD, 1992)

Design Methodology for Fault-Tolerant Systolic Array Architectures. - Michael Ogbonna Esonu; Asim J. Al-Khalili; Salim Hariri (ICPP (2), 1992)

Area efficient computing structures for concurrent error detection in systolic arrays. - Michael Ogbonna Esonu; Asim J. Al-Khalili; Salim Hariri (J. VLSI Signal Process., 1995)

Design techniques for fault-tolerant systolic arrays. - Michael Ogbonna Esonu; Asim J. Al-Khalili; Salim Hariri; Dhamin Al-Khalili (J. VLSI Signal Process., 1995)

A 2D micromachined accelerometer. - H. Ahmad; Asim J. Al-Khalili; L. Landsberger; M. Kahrizi (ICECS, 1996)

Energy delay analysis of partial product reduction methods for parallel multiplier implementation. - R. V. K. Pillai; Dhamin Al-Khalili; Asim J. Al-Khalili (ISLPED, 1996)

A Low Power Approach to Floating Point Adder Design. - R. V. K. Pillai; Dhamin Al-Khalili; Asim J. Al-Khalili (ICCD, 1997)

Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition. - R. V. K. Pillai; Dhamin Al-Khalili; Asim J. Al-Khalili (ISLPED, 1997)

A Low Power Floating Point Accumulator. - R. V. K. Pillai; Asim J. Al-Khalili; Dhamin Al-Khalili (VLSI Design, 1998)

An IEEE Compliant Floating Point MAF. - R. V. K. Pillai; Dhamin Al-Khalili; Asim J. Al-Khalili (VLSI, 1999)

Dynamic CMOS noise immunity estimation in submicron regime. - Adnan Kabbani; A. J. Al-Khalili (ISCAS (1), 1999)

Estimation of ground bounce effects on CMOS circuits. - Adnan Kabbani; A. J. Al-Khalili (ISCAS (1), 1999)

Power implications of precision limited arithmetic in floating point FIR filters. - R. V. K. Pillai; Dhamin Al-Khalili; Asim J. Al-Khalili (ISCAS (1), 1999)

Lossy Compression of Images Using Logic Minimization. - Jacob Augustine; William E. Lynch; Yuke Wang; Asim J. Al-Khalili (VLSI Design, 1999)

A CAD tool for first hand CMOS circuit selection. - P. Sun; A. J. Al-Khalili; Dhamin Al-Khalili (ICECS, 2000)

Low power floating point MAFs-a comparative study. - R. V. K. Pillai; S. Y. A. Shah; A. J. Al-Khalili; Dhamin Al-Khalili (ISSPA, 2001)

A Low Power Approach to Floating Point Adder Design for DSP Applications. - R. V. K. Pillai; Dhamin Al-Khalili; Asim J. Al-Khalili; S. Y. A. Shah (J. VLSI Signal Process., 2001)

Quadratic deferred-merge embedding algorithm for zero skew clock distribution network. - Haydar Saaied; Dhamin Al-Khalili; Asim J. Al-Khalili; Mohamed Nekili (Timing Issues in the Specification and Synthesis of Digital Systems, 2002)

Adaptive wire adjustment for bounded skew Clock Distribution Network. - Haydar Saaied; Dhamin Al-Khalili; Asim J. Al-Khalili; Mohamed Nekili (ASP-DAC, 2003)

Design of a 32-bit squarer - exploiting addition redundancy. - Asim J. Al-Khalili; Aiping Hu (ISCAS (5), 2003)

Technology-portable analytical model for DSM CMOS inverter transition-time estimation. - Adnan Kabbani; Dhamin Al-Khalili; Asim J. Al-Khalili (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Low-Power Constant-Coefficient Multiplier Generator. - Cheng-Yu Pai; Asim J. Al-Khalili; William E. Lynch (J. VLSI Signal Process., 2003)

New modulo decomposed residue-to-binary algorithm for general moduli sets. - Shaoqiang Bi; Wei Wang 003; Asim J. Al-Khalili (ICASSP (5), 2004)

Modulo deflation in (2n+1, 2n, 2n-1) converters. - Shaoqiang Bi; Wei Wang 003; Asim J. Al-Khalili (ISCAS (2), 2004)

Clock tree tuning using shortest paths polygon. - Haydar Saaied; Dhamin Al-Khalili; Asim J. Al-Khalili (SoCC, 2004)

An Area-Reduced Scheme for Modulo 2n-1 Addition/Subtraction. - Shaoqiang Bi; Warren J. Gross; Wei Wang 003; Asim J. Al-Khalili; M. N. S. Swamy (IWSOC, 2005)

Delay analysis of CMOS gates using modified logical effort model. - Adnan Kabbani; Dhamin Al-Khalili; Asim J. Al-Khalili (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree. - Haydar Saaied; Dhamin Al-Khalili; Asim J. Al-Khalili; Mohamed Nekili (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

A CAD Tool for Scalable, Variable Architecture Floating-Point Adder Generator. - A. J. Al-Khalili (AICCSA, 2006)

A CAD Tool for Generation of Synthesizable and Scalable Square of Binary Numbers. - Asim J. Al-Khalili (ICN/ICONS/MCL, 2006)

Zero skew differential clock distribution network. - Houman Zarrabi; Haydar Saaied; Asim J. Al-Khalili; Yvon Savaria (ISCAS, 2006)

Implementation of large-integer hardware multiplier in Xilinx FPGA. - Jacques Laurent Athow; Asim Jawad Al-Khalili (ICECS, 2008)

Dual-edge triggered energy recovery DCCER flip-flop for low energy applications. - Seyed Ebrahim Esmaeili; A. J. Al-Khalili; Glenn E. R. Cowan (ECCTD, 2009)

An interconnect-aware delay model for dynamic voltage scaling in NM technologies. - Houman Zarrabi; Asim J. Al-Khalili; Yvon Savaria (ACM Great Lakes Symposium on VLSI, 2009)

Estimation of energy performance in computing platforms. - Houman Zarrabi; Asim J. Al-Khalili; Yvon Savaria (ICECS, 2009)

Estimating required driver strength in the resonant clock generator. - Seyed Ebrahim Esmaeili; Asim J. Al-Khalili; Glenn E. R. Cowan (APCCAS, 2010)

An interconnect-aware Dynamic Voltage Scaling scheme for DSM VLSI. - Houman Zarrabi; Asim J. Al-Khalili; Yvon Savaria (ISCAS, 2010)

Pattern-Driven Clock Tree Routing with Via Minimization. - Ali M. Farhangi; Asim J. Al-Khalili; Dhamin Al-Khalili (ISVLSI, 2010)

Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks. - Seyed Ebrahim Esmaeili; A. J. Al-Khalili; Glenn E. R. Cowan (IET Comput. Digit. Tech., 2010)

Skew compensation in energy recovery clock distribution networks. - Seyed Ebrahim Esmaeili; Ali M. Farhangi; Asim J. Al-Khalili; Glenn E. R. Cowan (IET Comput. Digit. Tech., 2010)

Repeater insertion in power-managed VLSI systems. - Houman Zarrabi; Asim J. Al-Khalili; Yvon Savaria (ACM Great Lakes Symposium on VLSI, 2011)

Activity management in battery-powered embedded systems: A case study of ZigBee® WSN. - Houman Zarrabi; A. J. Al-Khalili; Yvon Savaria (ICECS, 2011)

SRAM read-assist scheme for high performanc low power applications. - Ali Valaee; Asim J. Al-Khalili (ISOCC, 2011)

Analysis of Resistive Open Defects in Drowsy SRAM Cells. - Afshin Nourivand; Asim J. Al-Khalili; Yvon Savaria (J. Electron. Test., 2011)

Clock tree structure with reduced wire length using the matched-delay skew compensation technique. - Seyed Ebrahim Esmaeili; Ali M. Farhangi; Asim J. Al-Khalili; Glenn E. R. Cowan (CCECE, 2012)

Dual-edge triggered sense amplifier flip-flop utilizing an improved scheme to reduce area, power, and complexity. - Seyed Ebrahim Esmaeili; Riadul Islam; Asim J. Al-Khalili; Glenn E. R. Cowan (ICECS, 2012)

High-performance low-power sensing scheme for nanoscale SRAMs. - Ali Valaee; A. J. Al-Khalili (IET Comput. Digit. Tech., 2012)

Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks. - Seyed Ebrahim Esmaeili; Asim J. Al-Khalili; Glenn E. R. Cowan (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures. - Afshin Nourivand; Asim J. Al-Khalili; Yvon Savaria (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Integrated Power and Clock Distribution Network. - Seyed Ebrahim Esmaeili; Asim J. Al-Khalili (IEEE Trans. Very Large Scale Integr. Syst., 2013)

10 GHz throughput FinFET dual-edge triggered flip-flops. - Seyed Ebrahim Esmaeili; Asim J. Al-Khalili (CCECE, 2014)

Vt-conscious repeater insertion in power-managed VLSI. - Houman Zarrabi; Asim J. Al-Khalili; Yvon Savaria (ISIC, 2014)

Design Intelligence for Interconnection Realization in Power-Managed SoCs. - Houman Zarrabi; A. J. Al-Khalili; Yvon Savaria (Computational Intelligence in Digital and Network Designs and Applications, 2015)

A finite element-guided mathematical surrogate modeling approach for assessing occupant injury trends across variations in simplified vehicular impact conditions. - P. R. Berthelson; Payam Ghassemi; J. W. Wood; G. G. Stubblefield; Asim J. Al-Khalili; M. D. Jones; Mark F. Horstemeyer; Souma Chowdhury; R. K. Prabhu (Medical Biol. Eng. Comput., 2021)