Performance and power optimization through data compression in Network-on-Chip architectures. - Reetuparna Das; Asit K. Mishra; Chrysostomos Nicopoulos; Dongkook Park; Vijaykrishnan Narayanan; Ravishankar R. Iyer 001; Mazin S. Yousif; Chita R. Das (HPCA, 2008)

Detection of Arcing in Low Voltage Distribution Systems. - Asit K. Mishra; Aurobinda Routray; Ashok Kumar Pradhan (ICIIS, 2008)

MIRA: A Multi-layered On-Chip Interconnect Router Architecture. - Dongkook Park; Soumya Eachempati; Reetuparna Das; Asit K. Mishra; Yuan Xie 001; Narayanan Vijaykrishnan; Chita R. Das (ISCA, 2008)

Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. - Reetuparna Das; Soumya Eachempati; Asit K. Mishra; Narayanan Vijaykrishnan; Chita R. Das (HPCA, 2009)

A case for dynamic frequency tuning in on-chip networks. - Asit K. Mishra; Reetuparna Das; Soumya Eachempati; Ravishankar R. Iyer 001; Narayanan Vijaykrishnan; Chita R. Das (MICRO, 2009)

A case for integrated processor-cache partitioning in chip multiprocessors. - Shekhar Srikantaiah; Reetuparna Das; Asit K. Mishra; Chita R. Das; Mahmut T. Kandemir (SC, 2009)

CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors. - Asit K. Mishra; Shekhar Srikantaiah; Mahmut T. Kandemir; Chita R. Das (SC, 2010)

Coordinated power management of voltage islands in CMPs. - Asit K. Mishra; Shekhar Srikantaiah; Mahmut T. Kandemir; Chita R. Das (SIGMETRICS, 2010)

Towards characterizing cloud backend workloads: insights from Google compute clusters. - Asit K. Mishra; Joseph L. Hellerstein; Walfredo Cirne; Chita R. Das (SIGMETRICS Perform. Evaluation Rev., 2010)

An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores. - Vinay Saripalli; Asit K. Mishra; Suman Datta; Vijaykrishnan Narayanan (DAC, 2011)

ACCESS: Smart scheduling for asymmetric cache CMPs. - Xiaowei Jiang; Asit K. Mishra; Li Zhao 002; Ravishankar R. Iyer 001; Zhen Fang 002; Sadagopan Srinivasan; Srihari Makineni; Paul Brett; Chita R. Das (HPCA, 2011)

Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. - Asit K. Mishra; Xiangyu Dong 001; Guangyu Sun 003; Yuan Xie 001; Narayanan Vijaykrishnan; Chita R. Das (ISCA, 2011)

A case for heterogeneous on-chip interconnects for CMPs. - Asit K. Mishra; Narayanan Vijaykrishnan; Chita R. Das (ISCA, 2011)

METE: meeting end-to-end QoS in multicores through system-wide resource management. - Akbar Sharifi; Shekhar Srikantaiah; Asit K. Mishra; Mahmut T. Kandemir; Chita R. Das (SIGMETRICS, 2011)

Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors. - Vinay Saripalli; Guangyu Sun 003; Asit K. Mishra; Yuan Xie 001; Suman Datta; Vijaykrishnan Narayanan (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

RAFT: A router architecture with frequency tuning for on-chip networks. - Asit K. Mishra; Aditya Yanamandra; Reetuparna Das; Soumya Eachempati; Ravi R. Iyer 001; Narayanan Vijaykrishnan; Chita R. Das (J. Parallel Distributed Comput., 2011)

Application-aware prefetch prioritization in on-chip networks. - Nachiappan Chidambaram Nachiappan; Asit K. Mishra; Mahmut T. Kandemir; Anand Sivasubramaniam; Onur Mutlu; Chita R. Das (PACT, 2012)

PEPON: performance-aware hierarchical power budgeting for NoC based multicores. - Akbar Sharifi; Asit K. Mishra; Shekhar Srikantaiah; Mahmut T. Kandemir; Chita R. Das (PACT, 2012)

Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs. - Adwait Jog; Asit K. Mishra; Cong Xu; Yuan Xie 001; Vijaykrishnan Narayanan; Ravishankar R. Iyer 001; Chita R. Das (DAC, 2012)

OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance. - Adwait Jog; Onur Kayiran; Nachiappan Chidambaram Nachiappan; Asit K. Mishra; Mahmut T. Kandemir; Onur Mutlu; Ravishankar R. Iyer 001; Chita R. Das (ASPLOS, 2013)

A heterogeneous multiple network-on-chip design: an application-aware approach. - Asit K. Mishra; Onur Mutlu; Chita R. Das (DAC, 2013)

Runnemede: An architecture for Ubiquitous High-Performance Computing. - Nicholas P. Carter; Aditya Agrawal; Shekhar Borkar; Romain Cledat; Howard David; Dave Dunning; Joshua B. Fryman; Ivan Ganev; Roger A. Golliver; Rob C. Knauerhase; Richard Lethin; Benoît Meister; et al. (HPCA, 2013)

Orchestrated scheduling and prefetching for GPGPUs. - Adwait Jog; Onur Kayiran; Asit K. Mishra; Mahmut T. Kandemir; Onur Mutlu; Ravishankar R. Iyer 001; Chita R. Das (ISCA, 2013)

Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks. - Amin Ansari; Asit K. Mishra; Jianping Xu; Josep Torrellas (HPCA, 2014)

A sparse matrix vector multiply accelerator for support vector machine. - Eriko Nurvitadhi; Asit K. Mishra; Debbie Marr (CASES, 2015)

Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities. - Ashutosh Pattnaik; Xulong Tang; Adwait Jog; Onur Kayiran; Asit K. Mishra; Mahmut T. Kandemir; Onur Mutlu; Chita R. Das (PACT, 2016)

Hardware accelerator for analytics of sparse data. - Eriko Nurvitadhi; Asit K. Mishra; Yu Wang 110; Ganesh Venkatesh; Debbie Marr (DATE, 2016)

Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC. - Eriko Nurvitadhi; Jaewoong Sim; David Sheffield; Asit K. Mishra; Krishnan Srivatsan; Debbie Marr (FPL, 2016)

Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC. - Eriko Nurvitadhi; David Sheffield; Jaewoong Sim; Asit K. Mishra; Ganesh Venkatesh; Debbie Marr (FPT, 2016)

ScalCore: Designing a core for voltage scalability. - Bhargava Gopireddy; Choungki Song; Josep Torrellas; Nam Sung Kim; Aditya Agrawal; Asit K. Mishra (HPCA, 2016)

Fine-grained accelerators for sparse machine learning workloads. - Asit K. Mishra; Eriko Nurvitadhi; Ganesh Venkatesh; Jonathan Pearce; Debbie Marr (ASP-DAC, 2017)

High performance binary neural networks on the Xeon+FPGA™ platform. - Duncan J. M. Moss; Eriko Nurvitadhi; Jaewoong Sim; Asit K. Mishra; Debbie Marr; Suchit Subhaschandra; Philip Heng Wai Leong (FPL, 2017)

WRPN: Training and Inference using Wide Reduced-Precision Networks. - Asit K. Mishra; Jeffrey J. Cook; Eriko Nurvitadhi; Debbie Marr (CoRR, 2017)

Low Precision RNNs: Quantizing RNNs Without Losing Accuracy. - Supriya Kapur; Asit K. Mishra; Debbie Marr (CoRR, 2017)

Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs. - Philip Colangelo; Nasibeh Nasiri; Eriko Nurvitadhi; Asit K. Mishra; Martin Margala; Kevin Nealis (FCCM, 2018)

Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only). - Philip Colangelo; Nasibeh Nasiri; Eriko Nurvitadhi; Asit K. Mishra; Martin Margala; Kevin Nealis (FPGA, 2018)

A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study. - Duncan J. M. Moss; Krishnan Srivatsan; Eriko Nurvitadhi; Piotr Ratuszniak; Chris Johnson; Jaewoong Sim; Asit K. Mishra; Debbie Marr; Suchit Subhaschandra; Philip Heng Wai Leong (FPGA, 2018)

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). - Eriko Nurvitadhi; Jeffrey J. Cook; Asit K. Mishra; Debbie Marr; Kevin Nealis; Philip Colangelo; Andrew C. Ling; Davor Capalija; Utku Aydonat; Sergey Y. Shumarayev; Aravind Dasu (FPGA, 2018)

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. - Eriko Nurvitadhi; Jeffrey J. Cook; Asit K. Mishra; Debbie Marr; Kevin Nealis; Philip Colangelo; Andrew C. Ling; Davor Capalija; Utku Aydonat; Aravind Dasu; Sergey Y. Shumarayev (FPL, 2018)

Apprentice: Using Knowledge Distillation Techniques To Improve Low-Precision Network Accuracy. - Asit K. Mishra; Debbie Marr (ICLR (Poster), 2018)

WRPN: Wide Reduced-Precision Networks. - Asit K. Mishra; Eriko Nurvitadhi; Jeffrey J. Cook; Debbie Marr (ICLR (Poster), 2018)

WRPN & Apprentice: Methods for Training and Inference using Low-Precision Numerics. - Asit K. Mishra; Debbie Marr (CoRR, 2018)

Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs. - Philip Colangelo; Nasibeh Nasiri; Asit K. Mishra; Eriko Nurvitadhi; Martin Margala; Kevin Nealis (CoRR, 2018)

Opportunistic computing in GPU architectures. - Ashutosh Pattnaik; Xulong Tang; Onur Kayiran; Adwait Jog; Asit K. Mishra; Mahmut T. Kandemir; Anand Sivasubramaniam; Chita R. Das (ISCA, 2019)

Accelerating Sparse Deep Neural Networks. - Asit K. Mishra; Jorge Albericio Latorre; Jeff Pool; Darko Stosic; Dusan Stosic; Ganesh Venkatesh; Chong Yu; Paulius Micikevicius (CoRR, 2021)

Exploiting Activation based Gradient Output Sparsity to Accelerate Backpropagation in CNNs. - Anup Sarma; Sonali Singh; Huaipan Jiang; Ashutosh Pattnaik; Asit K. Mishra; Vijaykrishnan Narayanan; Mahmut T. Kandemir; Chita R. Das (CoRR, 2021)

Recipes for Pre-training LLMs with MXFP8. - Asit K. Mishra; Dusan Stosic; Simon Layton (CoRR, 2025)