Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs. - Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Naudet; Christophe Forel (ETS, 2012)

Reduced code linearity testing of pipeline adcs in the presence of noise. - Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Naudet; Gerard Bret (VTS, 2013)

Reduced-Code Linearity Testing of Pipeline ADCs. - Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Naudet; Gerard Bret (IEEE Des. Test, 2013)

Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique. - Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Naudet (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. - Guillaume Renaud; Manuel J. Barragán; Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Le Gall; Hervé Naudet (J. Electron. Test., 2016)

16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC. - Bruno Vaz; Adrian Lynam; Bob Verbruggen; Asma Laraba; Conrado Mesadri; Ali Boumaalif; John McGrath; Umanath Kamath; Ronnie De La Torre; Alvin Manlapat; Daire Breathnach; Christophe Erdmann; et al. (ISSCC, 2017)

A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET. - James Hudner; Declan Carey; Ronan Casey; Kay Hearne; Pedro Wilson de Abreu Farias Neto; Ilias Chlis; Marc Erett; Chi Fung Poon; Asma Laraba; Hongtao Zhang 002; Sai Lalith Chaitanya Ambatipudi; David Mahashin; et al. (VLSI Circuits, 2018)

A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET. - Chi Fung Poon; Wenfeng Zhang; Junho Cho; Shaojun Ma; Yipeng Wang 003; Ying Cao 010; Asma Laraba; Eugene Ho; Winson Lin; Zhaoyin Daniel Wu; Kee Hian Tan; Parag Upadhyaya; et al. (VLSI Circuits, 2021)

A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET. - Chi Fung Poon; Wenfeng Zhang; Junho Cho; Shaojun Ma; Yipeng Wang 003; Ying Cao 010; Asma Laraba; Eugene Ho; Winson Lin; Zhaoyin Daniel Wu; Kee Hian Tan; Parag Upadhyaya; et al. (IEEE J. Solid State Circuits, 2022)