Using the inter- and intra-switch regularity in NoC switch testing. - Mohammad Hosseinabady; Atefe Dalirsani; Zainalabedin Navabi (DATE, 2007)

An Analytical Model for Reliability Evaluation of NoC Architectures. - Atefe Dalirsani; Mohammad Hosseinabady; Zainalabedin Navabi (IOLTS, 2007)

Structural Test for Graceful Degradation of NoC Switches. - Atefe Dalirsani; Stefan Holst; Melanie Elm; Hans-Joachim Wunderlich (ETS, 2011)

Structural Test and Diagnosis for Graceful Degradation of NoC Switches. - Atefe Dalirsani; Stefan Holst; Melanie Elm; Hans-Joachim Wunderlich (J. Electron. Test., 2012)

SAT-based code synthesis for fault-secure circuits. - Atefe Dalirsani; Michael A. Kochte; Hans-Joachim Wunderlich (DFTS, 2013)

On Covering Structural Defects in NoCs by Functional Tests. - Atefe Dalirsani; Nadereh Hatami; Michael E. Imhof; Marcus Eggenberger; Gert Schley; Martin Radetzki; Hans-Joachim Wunderlich (ATS, 2014)

Area-efficient synthesis of fault-secure NoC switches. - Atefe Dalirsani; Michael A. Kochte; Hans-Joachim Wunderlich (IOLTS, 2014)

Structural Software-Based Self-Test of Network-on-Chip. - Atefe Dalirsani; Michael E. Imhof; Hans-Joachim Wunderlich (VTS, 2014)

Intermittent and Transient Fault Diagnosis on Sparse Code Signatures. - Michael A. Kochte; Atefe Dalirsani; Andrea Bernabei; Martin Omaña 001; Cecilia Metra; Hans-Joachim Wunderlich (ATS, 2015)

Self-diagnosis in Network-on-Chips. - Atefe Dalirsani (2015)

Functional Diagnosis for Graceful Degradation of NoC Switches. - Atefe Dalirsani; Hans-Joachim Wunderlich (ATS, 2016)

Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. - Gert Schley; Atefe Dalirsani; Marcus Eggenberger; Nadereh Hatami; Hans-Joachim Wunderlich; Martin Radetzki (IEEE Trans. Computers, 2017)