Synergistic timing speculation for multi-threaded programs. - Atif Yasin; Jeff Jun Zhang; Hu Chen; Siddharth Garg; Sanghamitra Roy; Koushik Chakraborty (DAC, 2016)

Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis. - Tiankai Su; Cunxi Yu; Atif Yasin; Maciej J. Ciesielski (ISVLSI, 2017)

Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers. - Tiankai Su; Atif Yasin; Cunxi Yu; Maciej J. Ciesielski (ISCAS, 2018)

Rewriting Environment for Arithmetic Circuit Verification. - Cunxi Yu; Atif Yasin; Tiankai Su; Alan Mishchenko; Maciej J. Ciesielski (LPAR, 2018)

Spectral approach to verifying non-linear arithmetic circuits. - Cunxi Yu; Tiankai Su; Atif Yasin; Maciej J. Ciesielski (ASP-DAC, 2019)

Formal Verification of Integer Dividers: Division by a Constant. - Atif Yasin; Tiankai Su; Sébastien Pillement; Maciej J. Ciesielski (ISVLSI, 2019)

Functional Verification of Hardware Dividers using Algebraic Model. - Atif Yasin; Tiankai Su; Sébastien Pillement; Maciej J. Ciesielski (VLSI-SoC, 2019)

Improving software requirements reasoning by novices: a story-based approach. - Rubia Fatima; Affan Yasin; Lin Liu 001; Jianmin Wang 001; Wasif Afzal; Atif Yasin (IET Softw., 2019)

SPEAR: Hardware-based Implicit Rewriting for Square-root Circuit Verification. - Atif Yasin; Tiankai Su; Sébastien Pillement; Maciej J. Ciesielski (DATE, 2020)

Dual Approach to Solving SAT in Hardware. - Dinesh D. Narasimharaju; R. S. Suraj Rao; Akshaya Sandeep Waingade; Atif Yasin; Maciej J. Ciesielski (DTIS, 2020)

Formal Verification of Constrained Arithmetic Circuits using Computer Algebraic Approach. - Tiankai Su; Atif Yasin; Sébastien Pillement; Maciej J. Ciesielski (ISVLSI, 2020)

Understanding Algebraic Rewriting for Arithmetic Circuit Verification: A Bit-Flow Model. - Maciej J. Ciesielski; Tiankai Su; Atif Yasin; Cunxi Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Functional Verification of Arithmetic Circuits: Survey of Formal Methods. - Maciej J. Ciesielski; Atif Yasin; Jiteshri Dasari (DDECS, 2022)

Formal Verification of Divider Circuits by Hardware Reduction. - Atif Yasin; Tiankai Su; Sébastien Pillement; Maciej J. Ciesielski (SMACD, 2023)