Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits. - Atila Alvandpour; Per Larsson-Edefors; Christer Svensson (ISLPED, 1998)

Low power and low voltage CMOS digital circuit techniques. - Christer Svensson; Atila Alvandpour (ISLPED, 1998)

A leakage-tolerant multi-phase keeper for wide domino circuits. - Atila Alvandpour; Per Larsson-Edefors; Christer Svensson (ICECS, 1999)

GLMC: interconnect length estimation by growth-limited multifold clustering. - Atila Alvandpour; Per Larsson-Edefors; Christer Svensson (ISCAS, 2000)

A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder. - Henrik Eriksson; Per Larsson-Edefors; Atila Alvandpour (ISCAS (4), 2001)

A low-leakage dynamic multi-ported register file in 0.13mm CMOS. - Atila Alvandpour; Ram Krishnamurthy 001; Krishnamurthy Soumyanath; Shekhar Borkar (ISLPED, 2001)

A burn-in tolerant dynamic circuit technique. - Atila Alvandpour; Ram Krishnamurthy 001; Shekhar Borkar; A. Rahman; Clair Webb (CICC, 2002)

High-performance and low-power challenges for sub-70 nm microprocessor circuits. - Ram K. Krishnamurthy; Atila Alvandpour; Vivek De; Shekhar Borkar (CICC, 2002)

A sub-130-nm conditional keeper technique. - Atila Alvandpour; Ram K. Krishnamurthy; Krishnamurthy Soumyanath; Shekhar Y. Borkar (IEEE J. Solid State Circuits, 2002)

A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file. - Ram K. Krishnamurthy; Atila Alvandpour; Ganesh Balamurugan; Naresh R. Shanbhag; Krishnamurthy Soumyanath; Shekhar Y. Borkar (IEEE J. Solid State Circuits, 2002)

Bitline leakage equalization for sub-100nm caches. - Atila Alvandpour; Dinesh Somasekhar; Ram Krishnamurthy 001; Vivek De; Shekhar Borkar; Christer Svensson (ESSCIRC, 2003)

Low voltage sensing techniques and secondary design issues for sub-90nm caches. - Manoj Sinha; Steven Hsu; Atila Alvandpour; Wayne P. Burleson; Ram Krishnamurthy 001; Shekhar Borkar (ESSCIRC, 2003)

A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme. - Steven Hsu; Atila Alvandpour; Sanu Mathew; Shih-Lien Lu; Ram K. Krishnamurthy; Shekhar Borkar (IEEE J. Solid State Circuits, 2003)

A high density, low leakage, 5T SRAM for embedded caches. - Ingvar Carlson; Stefan Anderson; Sreedhar Natarajan; Atila Alvandpour (ESSCIRC, 2004)

A new mesochronous clocking scheme for synchronization in SoC. - Behzad Mesgarzadeh; Christer Svensson; Atila Alvandpour (ISCAS (2), 2004)

An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies. - Peter Caputa; Henrik Fredriksson; Martin Hansson; Stefan Back Andersson; Atila Alvandpour; Christer Svensson (PATMOS, 2004)

A low clock load conditional flip-flop. - Martin Hansson; Atila Alvandpour (SoCC, 2004)

A study of injection locking in ring oscillators. - Behzad Mesgarzadeh; Atila Alvandpour (ISCAS (6), 2005)

Structural Fault Diagnosis in Charge-Pump Based Phase-Locked Loops. - Aditya Sankar Medury; Ingvar Carlson; Atila Alvandpour; John Stensby (VLSI Design, 2005)

1.56 GHz On-chip Resonant Clocking in 130nm CMOS. - Martin Hansson; Behzad Mesgarzadeh; Atila Alvandpour (CICC, 2006)

First-Harmonic Injection-Locked Ring Oscillators. - Behzad Mesgarzadeh; Atila Alvandpour (CICC, 2006)

Curvature Compensated CMOS Bandgap with Sub 1V Supply. - Kevin Tom; Atila Alvandpour (DELTA, 2006)

A wide-tuning range 1.8 GHz quadrature VCO utilizing coupled ring oscillators. - Behzad Mesgarzadeh; Atila Alvandpour (ISCAS, 2006)

A Leakage Compensation Technique for Dynamic Latches and Flip-Flops in Nano-Scale CMOS. - Martin Hansson; Atila Alvandpour (SoCC, 2006)

A 24-mW 0.02-mm2 1.5-GHz DLL-Based Frequency Multiplier in 130-nm CMOS. - Behzad Mesgarzadeh; Atila Alvandpour (SoCC, 2006)

A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization. - Sriram R. Vangal; Yatin Vasant Hoskote; Nitin Borkar; Atila Alvandpour (IEEE J. Solid State Circuits, 2006)

Comparative Analysis of Process Variation Impact on Flip-Flop Power-Performance. - Martin Hansson; Atila Alvandpour (ISCAS, 2007)

Clocking. - Thucydides Xanthopoulos; Atila Alvandpour (ISSCC, 2007)

Jitter Characteristic in Charge Recovery Resonant Clock Distribution. - Behzad Mesgarzadeh; Martin Hansson; Atila Alvandpour (IEEE J. Solid State Circuits, 2007)

A 2-GHz 7-mW digital DLL-based frequency multiplier in 90-nm CMOS. - Behzad Mesgarzadeh; Atila Alvandpour (ESSCIRC, 2008)

A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode. - Behzad Mesgarzadeh; Atila Alvandpour (IEEE J. Solid State Circuits, 2009)

Utilizing Process Variations for Reference Generation in a Flash ADC. - Timmy Sundström; Atila Alvandpour (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A Class-D outphasing RF amplifier with harmonic suppression in 90nm CMOS. - Jonas Fritzin; Christer Svensson; Atila Alvandpour (ESSCIRC, 2010)

A 2.4 GS/s, 4.9 ENOB at Nyquist, single-channel pipeline ADC in 65nm CMOS. - Timmy Sundström; Christer Svensson; Atila Alvandpour (ESSCIRC, 2010)

Reliability study of a low-voltage Class-E power amplifier in 130nm CMOS. - Jonas Fritzin; Timmy Sundström; Ted Johansson; Atila Alvandpour (ISCAS, 2010)

EMI reduction by resonant clock distribution networks. - Behzad Mesgarzadeh; Atila Alvandpour (ISCAS, 2010)

A programmable-bandwidth amplifier for ultra-low-power switched-capacitor application. - Ali Fazli Yeknami; Mostafa Savadi Osgooei; Atila Alvandpour (ECCTD, 2011)

Power consumption bounds for SAR ADCs. - Dai Zhang; Christer Svensson; Atila Alvandpour (ECCTD, 2011)

A +32 dBm 1.85 GHz class-D outphasing RF PA in 130nm CMOS for WCDMA/LTE. - Jonas Fritzin; Christer Svensson; Atila Alvandpour (ESSCIRC, 2011)

A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices. - Dai Zhang; Ameya Bhide; Atila Alvandpour (ESSCIRC, 2011)

A multi-segment clocking scheme to reduce on-chip EMI. - Behzad Mesgarzadeh; Iman Esmaeil Zadeh; Atila Alvandpour (SoCC, 2011)

A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS. - Timmy Sundström; Christer Svensson; Atila Alvandpour (IEEE J. Solid State Circuits, 2011)

Phase Predistortion of a Class-D Outphasing RF Amplifier in 90 nm CMOS. - Jonas Fritzin; Ylva Jung; Per Niklas Landin; Peter Handel; Martin Enqvist; Atila Alvandpour (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 0.7-V 600-nW 87-dB SNDR DT-ΔΣ modulator with partly body-driven and switched op-amps for biopotential signal acquisition. - Ali Fazli Yeknami; Atila Alvandpour (BioCAS, 2012)

Reliability challenges in avionics due to silicon aging. - Behzad Mesgarzadeh; Ingemar Söderquist; Atila Alvandpour (DDECS, 2012)

A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s. - Dai Zhang; Atila Alvandpour (ESSCIRC, 2012)

A DLL-based injection-locked frequency synthesizer for WiMedia UWB. - Amin Ojani; Behzad Mesgarzadeh; Atila Alvandpour (ISCAS, 2012)

A Class-D stage with harmonic suppression and DLL-based phase generation. - Jonas Fritzin; Behzad Mesgarzadeh; Atila Alvandpour (MWSCAS, 2012)

A process variation tolerant DLL-based UWB frequency synthesizer. - Amin Ojani; Behzad Mesgarzadeh; Atila Alvandpour (MWSCAS, 2012)

A readout circuit for an uncooled IR camera with mismatch and self-heating compensation. - Daniel Svard; Christer Jansson; Atila Alvandpour (NORCHIP, 2012)

A 2.1 µW 76 dB SNDR DT-ΔΣ modulator for medical implant devices. - Ali Fazli Yeknami; Atila Alvandpour (NORCHIP, 2012)

Introduction to the Special Issue on the 37th European Solid-State Circuits Conference (ESSCIRC). - Atila Alvandpour; Patrick Reynaert; Trond Ytterdal (IEEE J. Solid State Circuits, 2012)

A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-µm CMOS for Medical Implant Devices. - Dai Zhang; Ameya Bhide; Atila Alvandpour (IEEE J. Solid State Circuits, 2012)

Design and Analysis of a Class-D Stage With Harmonic Suppression. - Jonas Fritzin; Christer Svensson; Atila Alvandpour (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Analysis of a 5.5-V Class-D Stage Used in +30-dBm Outphasing RF PAs in 130- and 65-nm CMOS. - Jonas Fritzin; Christer Svensson; Atila Alvandpour (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A quadrature UWB frequency synthesizer with dynamic settling-time calibration. - Amin Ojani; Behzad Mesgarzadeh; Atila Alvandpour (ISCAS, 2013)

A variable bandwidth amplifier for a dual-mode low-power ΔΣ modulator in cardiac pacemaker system. - Ali Fazli Yeknami; Atila Alvandpour (ISCAS, 2013)

A 0.5-V 250-nW 65-dB SNDR passive ΔΣ modulator for medical implant devices. - Ali Fazli Yeknami; Atila Alvandpour (ISCAS, 2013)

Critical path analysis of two-channel interleaved digital MASH ΔΣ modulators. - Ameya Bhide; Atila Alvandpour (NORCHIP, 2013)

Highly linear open-loop output driver design for high speed capacitive DACs. - Quoc-Tai Duong; Jerzy J. Dabrowski; Atila Alvandpour (NORCHIP, 2013)

A 0.7-V 400-nW fourth-order active-passive ΔΣ modulator with one active stage. - Ali Fazli Yeknami; Atila Alvandpour (VLSI-SoC, 2013)

Low-Power Low-Voltage ΔΣ Modulator Using Switched-Capacitor Passive Filters. - Ali Fazli Yeknami; Atila Alvandpour (VLSI-SoC (Selected Papers), 2013)

An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS. - Ameya Bhide; Omid Esmailzadeh Najari; Behzad Mesgarzadeh; Atila Alvandpour (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Least-Squares Phase Predistortion of a +30 dBm Class-D Outphasing RF PA in 65 nm CMOS. - Ylva Jung; Jonas Fritzin; Martin Enqvist; Atila Alvandpour (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Timing challenges in high-speed interleaved ΔΣ DACs. - Ameya Bhide; Atila Alvandpour (ISIC, 2014)

Low noise linear and wideband transconductance amplifier design for current-mode frontend. - Quoc-Tai Duong; Atila Alvandpour (ISIC, 2014)

A low-power direct IQ upconversion technique based on duty-cycled multi-phase sub-harmonic passive mixers for UWB transmitters. - Amin Ojani; Behzad Mesgarzadeh; Atila Alvandpour (ISIC, 2014)

A self-calibration technique for fast-switching frequency-hopped UWB synthesis. - Amin Ojani; Behzad Mesgarzadeh; Atila Alvandpour (MIXDES, 2014)

Design considerations for interface circuits to low-voltage piezoelectric energy harvesters. - Martin Nielsen-Lönn; J. Jacob Wikner; Atila Alvandpour (NORCHIP, 2014)

Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers. - Amin Ojani; Behzad Mesgarzadeh; Atila Alvandpour (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Low-Power DT ΔΣ Modulators Using SC Passive Filters in 65 nm CMOS. - Ali Fazli Yeknami; Fahad Qazi; Atila Alvandpour (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs. - Dai Zhang; Atila Alvandpour (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A fully-differential OTA in 28 nm UTBB FDSOI CMOS for PGA applications. - Prakash Harikumar; J. Jacob Wikner; Atila Alvandpour (ECCTD, 2015)

Design of efficient CMOS rectifiers for integrated piezo-MEMS energy-harvesting power management systems. - Martin Nielsen-Lönn; Prakash Harikumar; J. Jacob Wikner; Atila Alvandpour (ECCTD, 2015)

Power analysis for two-stage high resolution pipeline SAR ADC. - Kairang Chen; Quoc-Tai Duong; Atila Alvandpour (MIXDES, 2015)

An ultra-low-voltage OTA in 28 nm UTBB FDSOI CMOS using forward body bias. - Prakash Harikumar; J. Jacob Wikner; Atila Alvandpour (NORCAS, 2015)

An 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOS. - Ameya Bhide; Atila Alvandpour (IEEE J. Solid State Circuits, 2015)

Effect of Clock Duty-Cycle Error on Two-Channel Interleaved ΔΣ DACs. - Ameya Bhide; Amin Ojani; Atila Alvandpour (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers. - Amin Ojani; Behzad Mesgarzadeh; Atila Alvandpour (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Capacitive charge pump gain-stage with source follower buffers for pipelined SAR ADCs. - Kairang Chen; Atila Alvandpour (ISIC, 2016)

VCO-based ADCs for IoT applications. - Vishnu Unnikrishnan 001; Mark Vesterbacka; Atila Alvandpour (ISIC, 2016)

Design of a gain-stage for pipelined SAR ADC using capacitive charge pump. - Kairang Chen; Atila Alvandpour (MIXDES, 2016)

Asynchronous clock generator for a 14-bit two-stage pipelined SAR ADC in 0.18 μm CMOS. - Kairang Chen; Martin Nielsen-Lönn; Atila Alvandpour (NORCAS, 2016)

A 0.4-V Subnanowatt 8-Bit 1-kS/s SAR ADC in 65-nm CMOS for Wireless Sensor Applications. - Prakash Harikumar; J. Jacob Wikner; Atila Alvandpour (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS. - Dai Zhang; Atila Alvandpour (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Ring-oscillator-based timing generator for ultralow-power applications. - Pavel Angelov; Martin Nielsen-Lönn; Atila Alvandpour (NORCAS, 2017)

Self-oscillating multilevel switched-capacitor DC/DC converter for energy harvesting. - Martin Nielsen-Lönn; Pavel Angelov; J. Jacob Wikner; Atila Alvandpour (NORCAS, 2017)

Challenges for Miniaturised Energy Harvesting Sensor Systems. - Cristina Rusu; Sebastian Bader 002; Bengt Oelmann; Atila Alvandpour; Peter Enoksson; Tanja Braun; S. Tiedke; R. Dal Molin; G. Férin; P. Torvinen; Jessica Liljeholm (ICAIT, 2018)

A 10-bit 3.75-GS/s Binary-Weighted DAC with 58.6-pJ Energy Consumption in 65-nm CMOS. - Oscar Morales Chacon; J. Jacob Wikner; Atila Alvandpour; Liter Siek (NorCAS, 2020)

A Low Power Front-end for Biomedical Fluorescence Sensing Applications. - Seyed Ruhallah Qasemi; Maryam Rafati; Atila Alvandpour (NorCAS, 2020)

A 10b 1GS/s Inverter-Based Pipeline ADC in 65nm CMOS. - Timmy Sundström; Javad Bagheri Asli; Christer Svensson; Atila Alvandpour (NorCAS, 2020)

A digital switching scheme to reduce DAC glitches using code-dependent randomization. - Oscar Morales Chacon; J. Jacob Wikner; Atila Alvandpour; Liter Siek (NorCAS, 2021)

Comparative Analysis of CMOS Latch-Driver Circuits for Current-Steering Digital-to-Analog Converters. - Oscar Morales Chacon; J. Jacob Wikner; Atila Alvandpour; Liter Siek (MIXDES, 2022)

A Dynamic Range Extension Technique for Pseudo-Resistive Transimpedance Amplifiers Based on Two-Step Conversion. - Maryam Rafati; Seyed Ruhallah Qasemi; Atila Alvandpour (NorCAS, 2022)

A Review on Current-Steering DAC Design. - Xian Yang Lim; Wu Cong Lim; Boon Chiat Terence Teo; Venkadasamy Navaneethan; Chong Boon Tan; Nardi Utomo; Liter Siek; Atila Alvandpour (ICEIC, 2023)

A Parallel-Path Amplifier for Fast Output Settling. - Javad Bagheri Asli; Alireza Saberkari; Atila Alvandpour (NEWCAS, 2023)

A Modular System-level Testbench for 6G Beamforming Applications with Near Circuit-Level Fidelity. - Rikard Gannedahl; Javad Bagheri Asli; Henrik Sjöland; Atila Alvandpour (NEWCAS, 2023)

Extending Wireless Power Transfer Range for Self-Powered Micro Devices with mm-size Antenna. - Natachai Terawatsakul; Alireza Saberkari; Atila Alvandpour (NEWCAS, 2023)

Ultra Low Power ASK Demodulator/Manchester Decoder for Biomedical Applications. - Wei Cao; Alireza Saberkari; Atila Alvandpour (NorCAS, 2023)

A Low-Power Battery Charge and Discharge Protection Circuit for Bio-Implantable Sensors in 65nm CMOS. - Seyed Ruhallah Qasemi; Maryam Rafati; Atila Alvandpour (MIXDES, 2024)

High-Sensitivity Hybrid Compensated RF-to-DC Converter for Low-Power RFEH Applications. - Wei Cao; Alireza Saberkari; Atila Alvandpour (NorCAS, 2024)

Analysis and Design of a Reconfigurable RF-DC Rectifier for RF Energy Harvesting Systems. - André F. Ponchet; Javad Bagheri Asli; Alireza Saberkari; César W. V. Casañas; Atila Alvandpour; Ingemar Söderquist; Osamu Saotome (NorCAS, 2024)

A Low-Power Wireless Optical SoC for Fluorescence Monitoring. - Maryam Rafati; Seyed Ruhallah Qasemi; Wei Cao; Alireza Saberkari; Atila Alvandpour (ISCAS, 2025)

A Switched-Based Slew Rate and Gain Boosting Parallel-Path Amplifier for Switched-Capacitor Applications. - Javad Bagheri Asli; Alireza Saberkari; Atila Alvandpour (IEEE Trans. Very Large Scale Integr. Syst., 2025)