Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture. - Atin Mukherjee 001; Anindya Sundar Dhar (ISED, 2012)

Design of a Fault-Tolerant Conditional Sum Adder. - Atin Mukherjee 001; Anindya Sundar Dhar (VDAT, 2012)

New triple-transistor based defect-tolerant systems for reliable digital architectures. - Atin Mukherjee 001; Anindya Sundar Dhar (ISCAS, 2015)

Real-time fault-tolerance with hot-standby topology for conditional sum adder. - Atin Mukherjee 001; Anindya Sundar Dhar (Microelectron. Reliab., 2015)

Choice of granularity for reliable circuit design using dynamic reconfiguration. - Atin Mukherjee 001; Anindya Sundar Dhar (Microelectron. Reliab., 2016)

Triple transistor based fault tolerance for resource constrained applications. - Atin Mukherjee 001; Anindya Sundar Dhar (Microelectron. J., 2017)

Reliable VLSI Architecture Design Using Modulo-Quad-Transistor Redundancy Method. - Atin Mukherjee 001; Anindya Sundar Dhar (Circuits Syst. Signal Process., 2018)

Defect Tolerant Majority Voter Design Using Triple Transistor Redundancy. - Atin Mukherjee 001; Anindya Sundar Dhar (iSES, 2019)

Triple transistor based triple modular redundancy with embedded voter circuit. - Atin Mukherjee 001; Anindya Sundar Dhar (Microelectron. J., 2019)

Defect Tolerant Approach for Reliable Majority Voter Design Using Quadded Transistor Logic. - Atin Mukherjee 001 (TENCON, 2020)

A Self-Healing, High Performance and Low-Cost Radiation Hardened Latch Design. - Sandeep Kumar; Atin Mukherjee 001 (DFT, 2021)

A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing Latch for Radiation-Prone Applications. - Sandeep Kumar; Atin Mukherjee 001 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Design of Single Node Upset Resilient Latch for Low Power, Low Cost and Highly Robust Applications. - Anwesh Kumar Samal; Sandeep Kumar; Atin Mukherjee 001 (ITC-Asia, 2023)

FPGA-Based Low-Cost Architecture for R-Peak Detection and Heart-Rate Calculation Using Lifting-Based Discrete Wavelet Transform. - Anusaka Gon; Atin Mukherjee 001 (Circuits Syst. Signal Process., 2023)

High performance radiation-hardened SRAM cell design for robust applications. - Sandeep Kumar; Atin Mukherjee 001 (Microelectron. J., 2023)

Design of a low-area hardware architecture to predict early signs of sudden cardiac arrests. - Anusaka Gon; Atin Mukherjee 001 (Microprocess. Microsystems, 2024)

Low cost and high performance double-node upset resilient latch for low orbit space applications. - Sandeep Kumar; Atin Mukherjee 001 (Int. J. Circuit Theory Appl., 2024)