A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications. - Atsuo Hanami; Stefan Scotzniovsky; Kazuya Ishihara; Tetsuya Matsumura; Shin'ichi Takeuchi; Haruyuki Ohkuma; Koji Nishigaki; Hirokazu Suzuki; Masahiro Kazayama; Toyohiko Yoshida; Koji Tsuchihashi (CICC, 1998)

MPEG-2 4: 2: 2@HL encoder chip set. - Hidenori Sato; Hideo Ohira; Masahiko Kazayama; Ayako Harada; Masahiko Yoshimoto; Okikazu Tanno; Satoshi Kumaki; Kazuya Ishibara; Atsuo Hanami; Tetsuya Mutsumura (ISCAS, 2000)

A 99-mm2, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system. - Satoshi Kumaki; Hidehiro Takata; Yoshihide Ajioka; Tsukasa Ooishi; Kazuya Ishihara; Atsuo Hanami; Takaharu Tsuji; Yusuke Kanehira; Tetsuya Watanabe; Chikayoshi Morishima; Tomoaki Yoshizawa; Hidenori Sato; et al. (CICC, 2001)

A 99-mm2 0.7-W single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mb embedded DRAM for portable 422P@HL encoder system. - Satoshi Kumaki; Hidehiro Takata; Yoshihide Ajioka; Tsukasa Ooishi; Kazuya Ishihara; Atsuo Hanami; Takaharu Tsuji; Tetsuya Watanabe; Chikayoshi Morishima; Tomoaki Yoshizawa; Hidenori Sato; Shin-ichi Hattori; et al. (IEEE J. Solid State Circuits, 2002)