1.3- mu m CMOS/bipolar standard cell library for VLSI computers. - Takashi Hotta; Kouzaburou Kurita; Hideo Maejima; Masahiro Iwamura; Shigeya Tanaka; Tadaaki Bandoh; Tatsumi Yamauchi; Atsuo Hotta (IEEE J. Solid State Circuits, 1988)

Circuit technologies for BiCMOS VLSI's as computer elements. - Hideo Maejima; Tadaaki Bandoh; Yoji Nishio; Tadashi Fukushima; Masanori Odaka; Atsuo Hotta (ICCD, 1989)

A high performance BiCMOS 32-bit microprocessor. - Yasuhiro Nakatsuka; Takashi Hotta; Shigeya Tanaka; Tadaaki Bandoh; Ryuichi Satomura; Syuichi Nakagami; Tetsuo Nakano; Atsuo Hotta; Takashi Moriyama; Shigemi Adachi; Shoji Iwamoto (ICCD, 1989)

A 70-MHz 32-b microprocessor with 1.0- mu m BiCMOS macrocell library. - Takashi Hotta; Tadaaki Bandoh; Atsuo Hotta; Tetsuo Nakano; Shoji Iwamoto; Shigemi Adachi (IEEE J. Solid State Circuits, 1990)

110-GB/s simultaneous bidirectional transceiver logic synchronized with a system clock. - Toshiro Takahashi; Takashi Muto; Yuji Shirai; Fumihiko Shirotori; Yoshifumi Takada; Akira Yamagiwa; Akira Nishida; Atsuo Hotta; Tadashi Kiyuna (IEEE J. Solid State Circuits, 1999)

A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM. - Hiroaki Nambu; Kazuo Kanetani; Kaname Yamasaki; Keiichi Higeta; Masami Usami; Masahiko Nishiyama; Kenichi Ohhata; Fumihiko Arakawa; Takeshi Kusunoki; Kunihiko Yamaguchi; Atsuo Hotta; Noriyuki Homma (IEEE J. Solid State Circuits, 2000)

Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz. - Kenichi Ohhata; Fumihiko Arakawa; Takeshi Kusunoki; Hiroaki Nambu; Kazuo Kanetani; Kaname Yamasaki; Keiichi Higeta; Masami Usami; Masahiko Nishiyama; Kunihiko Yamaguchi; Noriyuki Homma; Atsuo Hotta (IEEE J. Solid State Circuits, 2000)

Synonym hit RAM - a 500-MHz CMOS SRAM macro with 576-bit parallel comparison and parity check functions. - Takeshi Suzuki; Keiichi Higeta; Yasuhiro Fujimura; Kazumasa Ando; Hiroaki Nambu; Ryo Yamagata; Atsuo Hotta; Kunihiko Yamaguchi (IEEE J. Solid State Circuits, 2000)