2-V/100-ns 1T/1C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and nonrelaxation reference cell. - Hiroshige Hirano; Toshiyuki Honda; Nobuyuki Moriwaki; Tetsuji Nakakuma; Atsuo Inoue; George Nakane; Shigeo Chaya; Tatsumi Sumi (IEEE J. Solid State Circuits, 1997)

The Parallel FDFM Processor Core Approach for Neural Networks. - Yuki Ago; Atsuo Inoue; Koji Nakano; Yasuaki Ito (ICNC, 2011)

Post-Quantum zk-SNARK for Arithmetic Circuits using QAPs. - Ken Naganuma; Masayuki Yoshino; Atsuo Inoue; Yukinori Matsuoka; Mineaki Okazaki; Noboru Kunihiro (AsiaJCIS, 2020)

Pocket Electrical Impedance Tomography (p-EIT) System With Wide Impedance Range Buffer- Mirrored Current Source (BMCS) With Assist of Filter-Trained Quasi-3-D Method for Functional Gastric-Shape Imaging. - Ridwan Wicaksono; Marlin Ramadhan Baidillah; Panji Nursetia Darma; Atsuo Inoue; Hideyuki Tsuji; Masahiro Takei (IEEE Trans. Instrum. Meas., 2021)

Post-quantum zk-SNARKs from QAPs. - Ken Naganuma; Masayuki Yoshino; Noboru Kunihiro; Atsuo Inoue; Yukinori Matsuoka; Mineaki Okazaki (Int. J. Inf. Comput. Secur., 2024)