95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm. - Shuhei Tanakamaru; Chinglin Hung; Atsushi Esumi; Mitsuyoshi Ito; Kai Li; Ken Takeuchi (ISSCC, 2011)

A 1/10000 lower error rate achievable SSD controller with Message-Passing Error Correcting Code architecture and Parity Area Combined scheme. - Kai Li; Mitsuyoshi Ito; Atsushi Esumi (CICC, 2013)