A high quality ADM LSI codec at 32 kbit/s for digital speech communications. - Naohisa Ohta; Kazunari Irie; Takehiko Uno; Atsushi Iwata; Tomonori Aoyama (ICASSP, 1982)

An 18-bit floating-point signal processor VLSI with an on-chip 512W dual-port RAM. - Hironori Yamauchi; Takao Kaneko; Tsutomu Kobayashi; Atsushi Iwata; Sadayasu Ono (ICASSP, 1985)

A 50ns floating-point signal processor VLSI. - Takao Kaneko; Hironori Yamauchi; Atsushi Iwata (ICASSP, 1986)

VLSI- A to D and D to A converters with multi-stage noise shaping modulators. - Kuniharu Uchimura; Toshio Hayashi; Tadakatsu Kimura; Atsushi Iwata (ICASSP, 1986)

A ring array processor architecture for highly parallel dynamic time warping. - Junichi Takahashi; Takashi Kimura; Sanshiro Hattori; Atsushi Iwata (IEEE Trans. Acoust. Speech Signal Process., 1986)

Oversampling A-to-D and D-to-A converters with multistage noise shaping modulators. - Kuniharu Uchimura; Toshio Hayashi; Tadakatsu Kimura; Atsushi Iwata (IEEE Trans. Acoust. Speech Signal Process., 1988)

Performance limits of mixed analog/digital circuits with scaled MOSFETs. - Eiichi Sano; Tsuneo Tsukahara; Atsushi Iwata (IEEE J. Solid State Circuits, 1988)

A 17 bit oversampling D-A conversion technology using multistage noise shaping. - Yasuyuki Matsuya; Kuniharu Uchimura; Atsushi Iwata; Takao Kaneko (IEEE J. Solid State Circuits, 1989)

ATM Connection and Traffic Management Schemes for Multimedia Internetworking. - Atsushi Iwata; N. Mori; Chinatsu Ikeda; Hiroshi Suzuki; Maximilian Ott (Commun. ACM, 1995)

QOS aggregation algorithms in hierarchical ATM networks. - Atsushi Iwata; Hiroshi Suzuki; Rauf Izmailov; Bhaskar Sengupta (ICC, 1998)

Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method. - Hiroshi Ando; Takashi Morie; Makoto Nagata; Atsushi Iwata (ICONIP, 1998)

Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation. - Souta Sakabayashi; Takashi Morie; Makoto Nagata; Atsushi Iwata (ICONIP, 1998)

A PWM signal processing core circuit based on a switched current integration technique. - Makoto Nagata; Jun Funakoshi; Atsushi Iwata (IEEE J. Solid State Circuits, 1998)

Measurements and analyses of substrate noise waveform in mixed signal IC environment. - Makoto Nagata; Yoji Kashima; Daisuke Tamura; Takashi Morie; Atsushi Iwata (CICC, 1999)

A Feature Associative Processor for Image Recognition Based on A-D merged Architecture. - Atsushi Iwata; Makoto Nagata; Hiroyuki Nakamoto; Noriaki Takeda; Mitsuru Homma; Hiroto Higashi; Takashi Morie (VLSI, 1999)

Scalable routing strategies for ad hoc wireless networks. - Atsushi Iwata; Ching-Chuan Chiang; Guangyu Pei; Mario Gerla; Tsu-Wei Chen (IEEE J. Sel. Areas Commun., 1999)

An arbitrary chaos generator core curcuit using PWM/PPM signals. - Kenichi Murakoshi; Takashi Morie; Makoto Nagata; Atsushi Iwata (ASP-DAC, 2000)

Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial. - Makoto Nagata; Atsushi Iwata (ASP-DAC, 2000)

A smart imager for the vision processing front-END. - Noriaki Takeda; Mitsuru Homma; Makoto Nagata; Takashi Morie; Atsushi Iwata (ASP-DAC, 2000)

Quantitative characterization of substrate noise for physical design guides in digital circuits. - Makoto Nagata; Jin Nagai; Takashi Morie; Atsushi Iwata (CICC, 2000)

Pulse modulation circuit architecture and its application to functional image sensors. - Atsushi Iwata; Makoto Nagata; Noriaki Takeda; Mitsuru Homma; Takashi Morie (ISCAS, 2000)

ATM Routing Algorithms for Multimedia Traffic in Private ATM Networks. - Rauf Izmailov; Atsushi Iwata; Bhaskar Sengupta (J. Heuristics, 2000)

A hierarchical multilayer QoS routing system with dynamic SLA management. - Atsushi Iwata; Norihito Fujita (IEEE J. Sel. Areas Commun., 2000)

Measurements and analyses of substrate noise waveform inmixed-signal IC environment. - Makoto Nagata; Jin Nagai; Takashi Morie; Atsushi Iwata (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Test circuits for substrate noise evaluation in CMOS digital ICs. - Makoto Nagata; Takafumi Ohmoto; Jin Nagai; Takashi Morie; Atsushi Iwata (ASP-DAC, 2001)

Adaptive and efficient multiple path pre-computation for QoS routing protocols. - Norihito Fujita; Atsushi Iwata (GLOBECOM, 2001)

Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. - Yoshitaka Murasaka; Makoto Nagata; Takafumi Ohmoto; Takashi Morie; Atsushi Iwata (ISQED, 2001)

An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures. - Takashi Morie; Tomohiro Matsuura; Makoto Nagata; Atsushi Iwata (NIPS, 2001)

A PWM analog memory programming circuit for floating-gate MOSFETs with 75-μs programming time and 11-bit updating resolution. - Shigeo Kinoshita; Takashi Morie; Makoto Nagata; Atsushi Iwata (IEEE J. Solid State Circuits, 2001)

Physical design guides for substrate noise reduction in CMOS digital circuits. - Makoto Nagata; Jin Nagai; Katsumasa Hijikata; Takashi Morie; Atsushi Iwata (IEEE J. Solid State Circuits, 2001)

A cellular-automaton-type image extraction algorithm and its implementation using an FPGA. - Teppei Nakano; Takashi Morie; Makoto Nagata; Atsushi Iwata (APCCAS (2), 2002)

Modeling substrate noise generation in CMOS digital integrated circuits. - Makoto Nagata; Takashi Morie; Atsushi Iwata (CICC, 2002)

Coarse-grain dynamic replication schemes for scalable content delivery networks. - Norihito Fujita; Nobuyuki Enomoto; Atsushi Iwata; Rauf Izmailov (GLOBECOM, 2002)

Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. - Makoto Nagata; Yoshitaka Murasaka; Youichi Nishimori; Takashi Morie; Atsushi Iwata (ASP-DAC/VLSI Design, 2002)

Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques. - Hiroshi Ando; Takashi Morie; Makoto Miyake; Makoto Nagata; Atsushi Iwata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A substrate noise analysis methodology for large-scale mixed-signal ICs. - Wen Kung Chu; Nishath K. Verghese; Heayn-Jun Chol; Kenji Shimazaki; Hiroyuki Tsujikawa; Shouzou Hirano; Shirou Doushoh; Makoto Nagata; Atsushi Iwata; Takafumi Ohmoto (CICC, 2003)

A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture. - Keisuke Korekado; Takashi Morie; Osamu Nomura; Hiroshi Ando; Teppei Nakano; Masakazu Matsugu; Atsushi Iwata (KES, 2003)

A High-Resolution CMOS Image Sensor with Hadamard Transform Function. - Kousuke Katayama; Atsushi Iwata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Design of multiple reverse spanning trees in next generation of Ethernet-VPNs. - Aleksandar Kolarov; Bhaskar Sengupta; Atsushi Iwata (GLOBECOM, 2004)

A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition. - Osamu Nomura; Takashi Morie; Keisuke Korekado; Masakazu Matsugu; Atsushi Iwata (KES, 2004)

Coarse-grain replica management strategies for dynamic replication of Web contents. - Norihito Fujita; Yuichi Ishikawa; Atsushi Iwata; Rauf Izmailov (Comput. Networks, 2004)

Gabor-Type Filtering using Transient States of Cellular Neural Networks. - Takashi Morie; Jun Umezawa; Atsushi Iwata (Intell. Autom. Soft Comput., 2004)

An analysis of interference in synchronous systems. - Tsutomu Yoshimura; Atsushi Iwata (IEICE Electron. Express, 2004)

A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture. - Keisuke Korekado; Takashi Morie; Osamu Nomura; Hiroshi Ando; Teppei Nakano; Masakazu Matsugu; Atsushi Iwata (J. Intell. Fuzzy Syst., 2004)

Global open ethernet (GOE) system and its performance evaluation. - Atsushi Iwata; Yoichi Hidaka; Masaki Umayabashi; Nobuyuki Enomoto; Akira Arutaki (IEEE J. Sel. Areas Commun., 2004)

A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations. - Osamu Nomura; Takashi Morie; Masakazu Matsugu; Atsushi Iwata (ICNC (3), 2005)

A 1V supply successive approximation ADC with rail-to-rail input voltage range. - Takeshi Yoshida; Miho Akagi; Mamoru Sasaki; Atsushi Iwata (ISCAS (1), 2005)

A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique. - Mitsuru Shiozaki; Toru Mukai; Masahiro Ono; Mamoru Sasaki; Atsushi Iwata (IEICE Trans. Electron., 2005)

A Cellular-Automaton-Type Region Extraction Algorithm and its FPGA Implementation. - Teppei Nakano; Takashi Morie; Makoto Nagata; Atsushi Iwata (J. Robotics Mechatronics, 2005)

A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip for Real-Time Robot Control with Multiprocessors. - Mitsuru Shiozaki; Toru Mukai; Masahiro Ono; Mamoru Sasaki; Atsushi Iwata (J. Robotics Mechatronics, 2005)

Stereo Matching Algorithm Using a Weighted Average of Costs Aggregated by Various Window Sizes. - Kan'ya Sasaki; Seiji Kameda; Atsushi Iwata (ACCV (2), 2006)

Proposal & demonstration of a new remote home-access system, softwire. - Hideo Yoshimi; Nobuyuki Enomoto; Chinryu Sai; Kazuo Takagi; Atsushi Iwata (CCNC, 2006)

ExpressEther - Ethernet-Based Virtualization Technology for Reconfigurable Hardware Platform. - Jun Suzuki 004; Yoichi Hidaka; Junichi Higuchi; Takashi Yoshikawa; Atsushi Iwata (Hot Interconnects, 2006)

FPGA Implementation of Resistive-Fuse Networks for Coarse Image-Region Segmentation. - Teppei Nakano; Takashi Morie; Hideaki Ishizu; Hiroshi Ando; Atsushi Iwata (Intell. Autom. Soft Comput., 2006)

20GHz uniform-phase uniform-amplitude standing-wave clock distribution. - Mitsuru Shiozaki; Mamoru Sasaki; Atsushi Mori; Atsushi Iwata; Hiroaki Ikeda (IEICE Electron. Express, 2006)

Carrier-Grade Ethernet Technologies for Next Generation Wide Area Ethernet. - Atsushi Iwata (IEICE Trans. Commun., 2006)

An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture. - Osamu Nomura; Takashi Morie; Keisuke Korekado; Teppei Nakano; Masakazu Matsugu; Atsushi Iwata (IEICE Trans. Electron., 2006)

A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory. - Kan'ya Sasaki; Takashi Morie; Atsushi Iwata (IEICE Trans. Electron., 2006)

Improving Ethernet Reliability and Stability Using Global Open Ethernet Technology. - Masaki Umayabashi; Yoichi Hidaka; Nobuyuki Enomoto; Daisaku Ogasahara; Kazuo Takagi; Atsushi Iwata; Akira Arutaki (IEICE Trans. Commun., 2006)

A 1 V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique. - Takeshi Yoshida; Yoshihiro Masui; Takayuki Mashimo; Mamoru Sasaki; Atsushi Iwata (IEICE Trans. Electron., 2006)

A study of interference in synchronous systems. - Tsutomu Yoshimura; Atsushi Iwata (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

NAT Traversal Technology of Reducing Load on Relaying Server for P2P Connections. - Hideo Yoshimi; Nobuyuki Enomoto; Zhenlong Cui; Kazuo Takagi; Atsushi Iwata (CCNC, 2007)

Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation. - Daisuke Kosaka; Makoto Nagata; Yoshitaka Murasaka; Atsushi Iwata (CICC, 2007)

12GHz Low-Area-Overhead Standing-Wave Clock Distribution with Inductively-Loaded and Coupled Technique. - Mamoru Sasaki; Mitsuru Shiozaki; Atsushi Mori; Atsushi Iwata; Hiroaki Ikeda (ISSCC, 2007)

On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications. - Tomio Sato; Atsuki Inoue; Tetsuyoshi Shiota; Tomoko Inoue; Yukihito Kawabe; Tetsutaro Hashimoto; Toshifumi Imamura; Yoshitaka Murasaka; Makoto Nagata; Atsushi Iwata (ISSCC, 2007)

Multilayer In-service Reconfiguration for Network Computing Systems. - Nobuharu Kami; Jun Suzuki 004; Yoichi Hidaka; Takashi Yoshikawa; Atsushi Iwata (NCA, 2007)

Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices. - Atsushi Iwata; Takeshi Yoshida; Mamoru Sasaki (IEICE Trans. Electron., 2007)

Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits. - Daisuke Kosaka; Makoto Nagata; Yoshitaka Murasaka; Atsushi Iwata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Chip-Level Substrate Coupling Analysis with Reference Structures for Verification. - Daisuke Kosaka; Makoto Nagata; Yoshitaka Murasaka; Atsushi Iwata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Crankback Signaling Extensions for MPLS and GMPLS RSVP-TE. - Adrian Farrel; Arun Satyanarayana; Atsushi Iwata; Norihito Fujita; Gerald R. Ash (RFC, 2007)

High-Speed, Short-Latency Multipath Ethernet for Data Center Area Communications. - Nobuyuki Enomoto; Hideyuki Shimonishi; Junichi Higuchi; Takashi Yoshikawa; Atsushi Iwata (GLOBECOM, 2008)

High-Speed, Short-Latency Multipath Ethernet Transport for Interconnections. - Nobuyuki Enomoto; Hideyuki Shimonishi; Junichi Higuchi; Takashi Yoshikawa; Atsushi Iwata (Hot Interconnects, 2008)

Off-the-path flow handling mechanism forhigh-speed and programmable traffic management. - Hideyuki Shimonishi; Takashi Yoshikawa; Atsushi Iwata (PRESTO, 2008)

Low power and low voltage chopper amplifier without LPF. - Yoshihiro Masui; Takeshi Yoshida; Atsushi Iwata (IEICE Electron. Express, 2008)

Building Hierarchical Switch Network Using OpenFlow. - Hideyuki Shimonishi; Hideya Ochiai; Nobuyuki Enomoto; Atsushi Iwata (INCoS, 2009)

A Neural Signal Detection Amplifier with Low-frequency Noise Suppression. - Takeshi Yoshida; Yoshihiro Masui; Ryoji Eki; Atsushi Iwata; Masayuki Yoshida; Kazumasa Uematsu (ISCAS, 2009)

A 1.0-V 10-b 30-MS/s 3.4-mW rail-to-rail pipelined ADC using a new front-end MDAC. - Kunihiko Gotoh; Hiroshi Ando; Atsushi Iwata (IEICE Electron. Express, 2009)

A 2.0 Vpp Input, 0.5 V Supply Delta Amplifier with A-to-D Conversion. - Yoshihiro Masui; Takeshi Yoshida; Atsushi Iwata (IEICE Trans. Electron., 2009)

A Neural Recording Amplifier with Low-Frequency Noise Suppression. - Takeshi Yoshida; Yoshihiro Masui; Ryoji Eki; Atsushi Iwata; Masayuki Yoshida; Kazumasa Uematsu (IEICE Trans. Electron., 2010)

A New Multi-Path Routing Methodology Based on Logit-Type Probability Assignment. - Yudai Honma; Masaki Aida; Hideyuki Shimonishi; Atsushi Iwata (IEICE Trans. Commun., 2011)

Background Calibration Techniques for Low-Power and High-Speed Data Conversion. - Atsushi Iwata; Yoshitaka Murasaka; Tomoaki Maeda; Takafumi Ohmoto (IEICE Trans. Electron., 2011)

Wide-Dynamic-Range APS-Based Silicon Retina With Brightness Constancy. - Kazuhiro Shimonomura; Seiji Kameda; Atsushi Iwata; Tetsuya Yagi (IEEE Trans. Neural Networks, 2011)

An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality. - Kazumi Aono; Atsushi Iwata; Hideki Takase; Kazuyoshi Takagi; Naofumi Takagi (HPCC/CSS/ICESS, 2014)

Differential equivalent time sampling receiver for breast cancer detection. - Yoshihiro Masui; Akihiro Toya; Mitsutoshi Sugawara; Tomoaki Maeda; Masahiro Ono; Yoshitaka Murasaka; Atsushi Iwata; Takamaro Kikkawa (BioCAS, 2017)

Investigation of phase noise and jitter in CMOS sampling clock generation circuits for time-domain breast cancer detection system. - Akihiro Toya; Yoshihiro Masui; Mitsutoshi Sugawara; Tomoaki Maeda; Masahiro Ono; Yoshitaka Murasaka; Atsushi Iwata; Takamaro Kikkawa (BioCAS, 2017)

Gaussian Monocycle Pulse Generator with Calibration Circuit for Breast Cancer Detection. - Yoshihiro Masui; Akihiro Toya; Mitsutoshi Sugawara; Tomoaki Maeda; Masahiro Ono; Yoshitaka Murasaka; Atsushi Iwata; Takamaro Kikkawa (BioCAS, 2018)

Shifting Clock Jitter and Phase Interval for Impulse-Radar-Based Breast Cancer Detection. - Akihiro Toya; Takamaro Kikkawa; Yoshihiro Masui; Mitsutoshi Sugawara; Hiroyuki Ito; Tomoaki Maeda; Masahiro Ono; Yoshitaka Murasaka; Toshifumi Imamura; Atsushi Iwata (BioCAS, 2019)

CMOS Gaussian Monocycle Pulse Transceiver for Radar-Based Microwave Imaging. - Takamaro Kikkawa; Yoshihiro Masui; Akihiro Toya; Hiroyuki Ito; Takuichi Hirano; Tomoaki Maeda; Masahiro Ono; Yoshitaka Murasaka; Toshifumi Imamura; Tsuyoshi Matsumaru; Michimasa Yamaguchi; Mitsutoshi Sugawara; et al. (IEEE Trans. Biomed. Circuits Syst., 2020)