A CT 2-2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction. - Mitsuya Fukazawa; Takashi Oshima; Masaki Fujiwara; Katsuki Tateyama; Atsushi Ochi; Alsubaie Raed; Tetsuo Matsui (IEEE J. Solid State Circuits, 2021)

A 16-bit SAR ADC with Capacitor Dielectric Relaxation Effect Canceler in a 22-nm Microcontroller for Multi-Input Channel Applications. - Tomohiko Ebata; Atsushi Ochi; Iori Sakai; Cheng Yuan; Takanobu Nimiya; Daiki Matsumoto; Qiaoyu Wang; Shinsuke Yoshimura; Tetsuo Matsui (A-SSCC, 2024)