Peel-the-box: a concept of switch-box routing and tractable problems. - Atsushi Takahashi 001; Yoji Kajitani (Integr., 1992)

Minimal acyclic forbidden minors for the family of graphs with bounded path-width. - Atsushi Takahashi 001; Shuichi Ueno; Yoji Kajitani (Discret. Math., 1994)

Mixed Searching and Proper-Path-Width. - Atsushi Takahashi 001; Shuichi Ueno; Yoji Kajitani (Theor. Comput. Sci., 1995)

Detailed-Routability of FPGAs with Extremal Switch-Block Structures. - Yasuhiro Takashima; Atsushi Takahashi 001; Yoji Kajitani (ED&TC, 1996)

Performance and reliability driven clock scheduling of sequential logic circuits. - Atsushi Takahashi 001; Yoji Kajitani (ASP-DAC, 1997)

Clock-tree routing realizing a clock-schedule for semi-synchronous circuits. - Atsushi Takahashi 001; Kazunori Inoue; Yoji Kajitani (ICCAD, 1997)

Air-Pressure-Model-Based Fast Algorithms for General Floorplan. - Tomonori Izumi; Atsushi Takahashi 001; Yoji Kajitani (ASP-DAC, 1998)

Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion. - Tomoyuki Yoda; Atsushi Takahashi 001; Yoji Kajitani (ASP-DAC, 1999)

Enumerating the min-cuts for applications to graph extraction under size constraints. - Kengo R. Azegami; Atsushi Takahashi 001; Y. Kajitan (ISCAS (6), 1999)

A practical clock tree synthesis for semi-synchronous circuits. - Masahiko Toyonaga; Keiichi Kurokawa; Takuya Yasui; Atsushi Takahashi 001 (ISPD, 2000)

Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. - Yoji Kajitani; Atsushi Takahashi 001; Kengo R. Azegami; Shigetoshi Nakatake (VLSI Design, 2000)

Clustering based fast clock scheduling for light clock-tree. - Makoto Saitoh; Masaaki Azuma; Atsushi Takahashi 001 (DATE, 2001)

Delay variation tolerant clock scheduling for semi-synchronous circuits. - Hidetoshi Matsumura; Atsushi Takahashi 001 (APCCAS (1), 2002)

An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm. - Kengo R. Azegami; Masato Inagi; Atsushi Takahashi 001; Yoji Kajitani (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A Semi-Synchronous Circuit Design Method by Clock Tree Modification. - Seiichiro Ishijima; Tetsuaki Utsumi; Tomohiro Oto; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling. - Keiichi Kurokawa; Takuya Yasui; Yoichi Matsumura; Masahiko Toyonaga; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A Clustering Based Fast Clock Schedule Algorithm for Light Clock-Trees. - Makoto Saitoh; Masaaki Azuma; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Optimal integer delay budgeting on directed acyclic graphs. - Elaheh Bozorgzadeh; Soheil Ghiasi; Atsushi Takahashi 001; Majid Sarrafzadeh (DAC, 2003)

Incremental Timing Budget Management in Programmable Systems. - Elaheh Bozorgzadeh; Soheil Ghiasi; Atsushi Takahashi 001; Majid Sarrafzadeh (ERSA, 2004)

Optimal integer delay-budget assignment on directed acyclic graphs. - Elaheh Bozorgzadeh; Soheil Ghiasi; Atsushi Takahashi 001; Majid Sarrafzadeh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

A global routing method for 2-layer ball grid array packages. - Yukiko Kubo; Atsushi Takahashi 001 (ISPD, 2005)

Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion. - Yukihide Kohira; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages. - Yukiko Kubo; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits. - Bakhtiar Affendi Rosdi; Atsushi Takahashi 001 (APCCAS, 2006)

Low area pipelined circuits by multi-clock cycle paths and clock scheduling. - Bakhtiar Affendi Rosdi; Atsushi Takahashi 001 (ASP-DAC, 2006)

Monotonic parallel and orthogonal routing for single-layer ball grid array packages. - Yoichi Tomioka; Atsushi Takahashi 001 (ASP-DAC, 2006)

Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems. - Yukihide Kohira; Chikaaki Kodama; Kunihiro Fujiyoshi; Atsushi Takahashi 001 (ISCAS, 2006)

Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits. - Bakhtiar Affendi Rosdi; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Practical Fast Clock-Schedule Design Algorithms. - Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages. - Yoichi Tomioka; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages. - Yukiko Kubo; Atsushi Takahashi 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework. - Yukihide Kohira; Atsushi Takahashi 001 (ISCAS, 2007)

Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization. - Yukihide Kohira; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements. - Bakhtiar Affendi Rosdi; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A semi-monotonic routing method for fanin type Ball Grid Array packages. - Yoichi Tomioka; Atsushi Takahashi 001 (APCCAS, 2008)

Routability driven modification method of monotonic via assignment for 2-layer Ball Grid Array packages. - Yoichi Tomioka; Atsushi Takahashi 001 (ASP-DAC, 2008)

ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems. - Masato Inagi; Yasuhiro Takashima; Yuichi Nakamura 002; Atsushi Takahashi 001 (ISCAS, 2008)

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems. - Masato Inagi; Yasuhiro Takashima; Yuichi Nakamura 002; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework. - Yukihide Kohira; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A Fast Clock Scheduling for Peak Power Reduction in LSI. - Yosuke Takahashi; Yukihide Kohira; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A Fast Longer Path Algorithm for Routing Grid with Obstacles Using Biconnectivity Based Length Upper Bound. - Yukihide Kohira; Suguru Suehiro; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework. - Yukihide Kohira; Shuhei Tani; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages. - Yoichi Tomioka; Yoshiaki Kurata; Yukihide Kohira; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages. - Yoichi Tomioka; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

CAFE Router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles. - Yukihide Kohira; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

RRA-based multi-objective optimization to mitigate the worst cases of placement. - Yiqiang Sheng; Atsushi Takahashi 001; Shuichi Ueno (ASICON, 2011)

Relay-Race Algorithm: A Novel Heuristic Approach to VLSI/PCB Placement. - Yiqiang Sheng; Atsushi Takahashi 001; Shuichi Ueno (ISVLSI, 2011)

Single-Layer Trunk Routing Using Minimal 45-Degree Lines. - Kyosuke Shinoda; Yukihide Kohira; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Foreword. - Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

An any-angle routing method using quasi-Newton method. - Yukihide Kohira; Atsushi Takahashi 001 (ASP-DAC, 2012)

Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control. - Chikaaki Kodama; Hirotaka Ichikawa; Koichi Nakayama; Toshiya Kotani; Shigeki Nojima; Shoji Mimotogi; Shinji Miyamoto; Atsushi Takahashi 001 (ASP-DAC, 2013)

Dawn of computer-aided design: from graph-theory to place and route. - Atsushi Takahashi 001 (ISPD, 2013)

A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization. - Yiqiang Sheng; Atsushi Takahashi 001 (IPSJ Trans. Syst. LSI Des. Methodol., 2013)

2-SAT based linear time optimum two-domain clock skew scheduling. - Yukihide Kohira; Atsushi Takahashi 001 (ASP-DAC, 2014)

A fast process variation and pattern fidelity aware mask optimization algorithm. - Ahmed Awad 002; Atsushi Takahashi 001; Satoshi Tanaka; Chikaaki Kodama (ICCAD, 2014)

Positive Semidefinite Relaxation and Approximation Algorithm for Triple Patterning Lithography. - Tomomi Matsui; Yukihide Kohira; Chikaaki Kodama; Atsushi Takahashi 001 (ISAAC, 2014)

2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework. - Yukihide Kohira; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A Novel High-Performance Heuristic Algorithm with Application to Physical Design Optimization. - Yiqiang Sheng; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography. - Yukihide Kohira; Tomomi Matsui; Yoko Yokoyama; Chikaaki Kodama; Atsushi Takahashi 001; Shigeki Nojima; Satoshi Tanaka (ASP-DAC, 2015)

Effective two-dimensional pattern generation for self-aligned double patterning. - Takeshi Ihara; Atsushi Takahashi 001; Chikaaki Kodama (ISCAS, 2015)

A Length Matching Routing Algorithm for Set-Pair Routing Problem. - Yuta Nakatani; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods. - Chikaaki Kodama; Hirotaka Ichikawa; Koichi Nakayama; Fumiharu Nakajima; Shigeki Nojima; Toshiya Kotani; Takeshi Ihara; Atsushi Takahashi 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Manufacturability-aware mask assignment in multiple patterning lithography. - Yukihide Kohira; Atsushi Takahashi 001; Tomomi Matsui; Chikaaki Kodama; Shigeki Nojima; Satoshi Tanaka (APCCAS, 2016)

A fast manufacturability aware Optical Proximity Correction (OPC) algorithm with adaptive wafer image estimation. - Ahmed Awad 002; Atsushi Takahashi 001; Chikaaki Kodama (DATE, 2016)

Grid-based Self-Aligned Quadruple Patterning aware two dimensional routing pattern. - Takeshi Ihara; Toshiyuki Hongo; Atsushi Takahashi 001; Chikaaki Kodama (DATE, 2016)

A Fast Mask Manufacturability and Process Variation Aware OPC Algorithm with Exploiting a Novel Intensity Estimation Model. - Ahmed Awad 002; Atsushi Takahashi 001; Chikaaki Kodama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A Routing Method Using Directed Grid-Graph for Self-Aligned Quadruple Patterning. - Takeshi Ihara; Toshiyuki Hongo; Atsushi Takahashi 001; Chikaaki Kodama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement. - Ahmed Awad 002; Atsushi Takahashi 001; Satoshi Tanaka; Chikaaki Kodama (IPSJ Trans. Syst. LSI Des. Methodol., 2017)

A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling. - Ahmed Awad 002; Atsushi Takahashi 001; Satoshi Tanaka; Chikaaki Kodama (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses. - Atsushi Takahashi 001; Shimpei Sato; Hiroki Ogura; Yu-Min Sung; Ting-Chi Wang (ISVLSI, 2018)

A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution. - Shimpei Sato; Eijiro Sassa; Yuta Ukon; Atsushi Takahashi 001 (ISCAS, 2019)

A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution. - Shimpei Sato; Eijiro Sassa; Yuta Ukon; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections. - Shimpei Sato; Kano Akagi; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020)

Message from the Editor-in-Chief. - Atsushi Takahashi 001 (IPSJ Trans. Syst. LSI Des. Methodol., 2020)

Report on the 28th Asia and South Pacific Design Automation Conference. - Atsushi Takahashi 001 (IEEE Des. Test, 2023)

BCA Channel Routing to Minimize Wirelength for Generalized Channel Problem. - Zezhong Wang; Masayuki Shimoda; Atsushi Takahashi 001 (ISCAS, 2024)

Wirelength Minimization by Gap Swap-Flip in Gridless Gap Channel Routing. - Masayuki Shimoda; Atsushi Takahashi 001 (ISOCC, 2024)

Two-layer Bottleneck Channel Track Assignment for Analog VLSI. - Kazuya Taniguchi; Satoshi Tayu; Atsushi Takahashi 001; Mathieu Molongo; Makoto Minami; Katsuya Nishioka (IPSJ Trans. Syst. LSI Des. Methodol., 2024)

Gap Channel Routing with Fixed Wires. - Masayuki Shimoda; Atsushi Takahashi 001; Kosuke Yanagidaira; Mikiko Hirai; Toshikazu Watanabe; Toshimitsu Iwasawa; Chikaaki Kodama (ISCAS, 2025)

Gridless Gap Channel Routing with Variable-Width Wires. - Masayuki Shimoda; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)

A Fast Three-Layer One-Side Bottleneck Channel Routing with Layout Constraints Using ILP. - Kazuya Taniguchi; Satoshi Tayu; Atsushi Takahashi 001; Mathieu Molongo; Makoto Minami; Katsuya Nishioka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)

SDG Channel Routing to Minimize Wirelength for Generalized Channel. - Zezhong Wang; Masayuki Shimoda; Atsushi Takahashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)

Gridless Gap Channel Routing to Minimize Wirelength. - Masayuki Shimoda; Atsushi Takahashi 001 (IPSJ Trans. Syst. LSI Des. Methodol., 2025)