A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers. - Atsutake Kosuge; Wataru Mizuhara; Noriyuki Miura; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (CICC, 2012)

A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line. - Won-Joo Yun; Shinya Nakano; Wataru Mizuhara; Atsutake Kosuge; Noriyuki Miura; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2012)

A 0.15mm-thick non-contact connector for MIPI using vertical directional coupler. - Wataru Mizuhara; Tsunaaki Shidei; Atsutake Kosuge; Tsutomu Takeya; Noriyuki Miura; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2013)

30.6 An electromagnetic clip connector for in-vehicle LAN to reduce wire harness weight by 30%. - Atsutake Kosuge; Shu Ishizuka; Lechang Liu; Akira Okada; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (ISSCC, 2014)

A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler. - Atsutake Kosuge; Wataru Mizuhara; Tsunaaki Shidei; Tsutomu Takeya; Noriyuki Miura; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2014)

Design and analysis for ThruChip design for manufacturing (DFM). - Li-Chung Hsu; Yasuhiro Take; Atsutake Kosuge; So Hasegawa; Junichiro Kadamoto; Tadahiro Kuroda (ASP-DAC, 2015)

Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interface. - Akira Okada; Abdul Raziz Junaidi; Yasuhiro Take; Atsutake Kosuge; Tadahiro Kuroda (ASP-DAC, 2015)

24.4 A 6.5Gb/s Shared bus using electromagnetic connectors for downsizing and lightening satellite processor system by 60%. - Atsutake Kosuge; Shu Ishizuka; Marni Abe; Satoshi Ichikawa; Tadahiro Kuroda (ISSCC, 2015)

10.1 A 6Gb/s 6pJ/b 5mm-distance non-contact interface for modular smartphones using two-fold transmission-line coupler and EMC-qualified pulse transceiver. - Atsutake Kosuge; Shu Ishizuka; Junichiro Kadomoto; Tadahiro Kuroda (ISSCC, 2015)

Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory. - Atsutake Kosuge; Junki Hashiba; Toru Kawajiri; So Hasegawa; Tsunaaki Shidei; Hiroki Ishikuro; Tadahiro Kuroda; Ken Takeuchi (VLSIC, 2015)

A Study of Physical Design Guidelines in ThruChip Inductive Coupling Channel. - Li-Chung Hsu; Junichiro Kadomoto; So Hasegawa; Atsutake Kosuge; Yasuhiro Take; Tadahiro Kuroda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Analysis and Design of an 8.5-Gb/s/Link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers. - Atsutake Kosuge; Shu Ishizuka; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Analytical thruchip inductive coupling channel design optimization. - Li-Chung Hsu; Junichiro Kadomoto; So Hasegawa; Atsutake Kosuge; Yasuhiro Take; Tadahiro Kuroda (ASP-DAC, 2016)

A 1 Tb/s/mm2 inductive-coupling side-by-side chip link. - So Hasegawa; Junichiro Kadomoto; Atsutake Kosuge; Tadahiro Kuroda (ESSCIRC, 2016)

Analysis and Evaluation of Electromagnetic Interference between ThruChip Interface and LC-VCO. - Junichiro Kadomoto; So Hasegawa; Yusuke Kiuchi; Atsutake Kosuge; Tadahiro Kuroda (IEICE Trans. Electron., 2016)

An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories. - Atsutake Kosuge; Junki Hashiba; Toru Kawajiri; So Hasegawa; Tsunaaki Shidei; Hiroki Ishikuro; Tadahiro Kuroda; Ken Takeuchi (IEEE J. Solid State Circuits, 2016)

A 6 Gb/s 6 pJ/b 5 mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and High EMC Tolerant Pulse Transceiver. - Atsutake Kosuge; Junichiro Kadomoto; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2016)

A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver. - Atsutake Kosuge; Akira Okada; Masao Taguchi; Hiroki Ishikuro; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A 4.8x Faster FPGA-Based Iterative Closest Point Accelerator for Object Pose Estimation of Picking Robot Applications. - Atsutake Kosuge; Keisuke Yamamoto; Yukinori Akamine; Taizo Yamawaki; Takashi Oshima (FCCM, 2019)

An Object-Pose Estimation Acceleration Technique for Picking Robot Applications by Using Graph-Reusing k-NN Search. - Atsutake Kosuge; Takashi Oshima (GC, 2019)

A 1200×1200 8-Edges/Vertex FPGA-Based Motion-Planning Accelerator for Dual-Arm-Robot Manipulation Systems. - Atsutake Kosuge; Takashi Oshima (VLSI Circuits, 2020)

A 5-GHz 0.15-mm2 Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna. - Saito Shibata; Reiji Miura; Yoshiki Sawabe; Kota Shiba; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (A-SSCC, 2021)

A 16 nJ/Classification FPGA-Based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net. - Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

An SoC-FPGA-Based Iterative-Closest-Point Accelerator Enabling Faster Picking Robots. - Atsutake Kosuge; Keisuke Yamamoto; Yukinori Akamine; Takashi Oshima (IEEE Trans. Ind. Electron., 2021)

POISON: Human Pose Estimation in Insufficient Lighting Conditions Using Sensor Fusion. - Viviana Crescitelli; Atsutake Kosuge; Takashi Oshima (IEEE Trans. Instrum. Meas., 2021)

A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation. - Reiji Miura; Saito Shibata; Masahiro Usui; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (ASP-DAC, 2022)

A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network. - Yao-Chung Hsu; Atsutake Kosuge; Rei Sumikawa; Kota Shiba; Mototsugu Hamada; Tadahiro Kuroda (HCS, 2022)

A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers. - Kota Shiba; Mitsuji Okada; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (HCS, 2022)

A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic. - Saito Shibata; Yoshiki Sawabe; Kota Shiba; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (ICECS 2022, 2022)

A 7 Gb/s Micro Rotatable Transmission Line Coupler with Deep Proximity Coupling Mode and Ground Shielding Vias. - Ximing Wang; Atsutake Kosuge; Yasuhiro Hayashi; Mototsugu Hamada; Tadahiro Kuroda (ICECS 2022, 2022)

Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format. - Kota Shiba; Mitsuji Okada; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (NEWCAS, 2022)

An Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion Technique. - Lixing Yu; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (SAS, 2022)

A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System. - Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC. - Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2022)

A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network. - Atsutake Kosuge; Yao-Chung Hsu; Mototsugu Hamada; Tadahiro Kuroda (IEEE Open J. Circuits Syst., 2022)

Proximity Wireless Communication Technologies: An Overview and Design Guidelines. - Atsutake Kosuge; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

mmWave-YOLO: A mmWave Imaging Radar-Based Real-Time Multiclass Object Recognition System for ADAS Applications. - Atsutake Kosuge; Satoshi Suehiro; Mototsugu Hamada; Tadahiro Kuroda (IEEE Trans. Instrum. Meas., 2022)

A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network. - Yao-Chung Hsu; Atsutake Kosuge; Rei Sumikawa; Kota Shiba; Mototsugu Hamada; Tadahiro Kuroda (ASP-DAC, 2023)

A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS. - Rei Sumikawa; Kota Shiba; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (ASP-DAC, 2023)

An Occlusion-Resilient mmWave Imaging Radar-Based Object Recognition System Using Synthetic Training Data Generation Technique. - Eitaro Kobayashi; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IECON, 2023)

A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network. - Dongzhu Li; Yao-Chung Hsu; Rei Sumikawa; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (ISCAS, 2023)

Analysis and Design of a 7 Gb/s Rotatable Non-contact Connector with Grid Array Package Application. - Ximing Wang; Atsutake Kosuge; Yasuhiro Hayashi; Kota Shiba; Mototsugu Hamada; Tadahiro Kuroda (NEWCAS, 2023)

A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application. - Atsutake Kosuge; Rei Sumikawa; Yao-Chung Hsu; Kota Shiba; Mototsugu Hamada; Tadahiro Kuroda (VLSI Technology and Circuits, 2023)

A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver. - Kota Shiba; Mitsuji Okada; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2023)

A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum. - Atsutake Kosuge; Yao-Chung Hsu; Rei Sumikawa; Mototsugu Hamada; Tadahiro Kuroda; Tomoe Ishikawa (IEEE Micro, 2023)

Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface. - Kota Shiba; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEICE Trans. Electron., 2023)

Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS. - Kota Shiba; Mitsuji Okada; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 250.3μW Versatile Sound Feature Extractor Using 1024-point FFT 64-ch LogMel Filter in 40nm CMOS. - Akiho Kawada; Kenji Kobayashi; Jaewon Shin; Rei Sumikawa; Mototsugu Hamada; Atsutake Kosuge (APCCAS, 2024)

Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions. - Dongzhu Li; Tianqi Zhao; Kenji Kobayashi; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (ISCAS, 2024)

A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA. - Dongzhu Li; Zhijie Zhan; Rei Sumikawa; Mototsugu Hamada; Atsutake Kosuge; Tadahiro Kuroda (IEICE Trans. Electron., 2024)

A Coarse- and Fine-Grained LUT Segmentation Method Enabling Single FPGA Implementation of Wired-Logic DNN Processor. - Yuxuan Pan; Dongzhu Li; Mototsugu Hamada; Atsutake Kosuge (ASP-DAC, 2025)

Can the Agile-Chip Platform Carve Out a Niche Between ASICs and FPGAs? - Hideharu Amano; Atsutake Kosuge; Hirofumi Sumi; Naonobu Shimamoto; Yukinori Ochiai; Yurie Inoue; Tohru Mogami; Yoshio Mita; Makoto Ikeda (COOL CHIPS, 2025)

An SoC Design and Fabrication Hands-On Educational Course within One Week Using Structured ASIC. - Hideharu Amano; Atsutake Kosuge; Hirofumi Sumi; Naonobu Shimamoto; Yukinori Ochiai; Yurie Inoue; Tohru Mogami; Yoshio Mita; Makoto Ikeda (ISCAS, 2025)

A 83.7% Resource Reduced FPGA-based Wired-Logic DNN Processor by Using Mixed-Precision Module Embedding Into Non-Linear Function LUT. - Yuxuan Pan; Mototsugu Hamada; Atsutake Kosuge (ISCAS, 2025)

13.6 A Via-Programmable DNN-Processor Fabrication Toward 1/40th Mask Cost. - Jaewon Shin; Rei Sumikawa; Dongzhu Li; Mototsugu Hamada; Atsutake Kosuge (ISSCC, 2025)

Analysis and Design of Coarse and Fine Segmented LUT Implementation for FPGA-Based Resource Efficient Wired-Logic DNN Processors. - Yuxuan Pan; Dongzhu Li; Mototsugu Hamada; Atsutake Kosuge (IEICE Trans. Electron., 2025)

Agile-X: A Structured-ASIC Created With a Mask-Less Lithography System Enabling Low-Cost and Agile Chip Fabrication. - Atsutake Kosuge; Hirofumi Sumi; Naonobu Shimamoto; Yukinori Ochiai; Yurie Inoue; Hideharu Amano; Tohru Mogami; Yoshio Mita; Makoto Ikeda; Tadahiro Kuroda (IEEE Trans. Very Large Scale Integr. Syst., 2025)