Optical Interconnect Opportunities for Future Server Memory Systems. - Yasunao Katayama; Atsuya Okazaki (HPCA, 2007)

Universal optical multi-drop bus for heterogeneous memory architecture. - Atsuya Okazaki; Yasunao Katayama; Seiji Munetoh (Conf. Computing Frontiers, 2011)

Software-defined massive multicore networking via freespace optical interconnect. - Yasunao Katayama; Atsuya Okazaki; Nobuyuki Ohba (Conf. Computing Frontiers, 2013)

Non-intrusive Scalable Memory Access Tracer. - Nobuyuki Ohba; Seiji Munetoh; Atsuya Okazaki; Yasunao Katayama (QEST, 2014)

NVM Weight Variation Impact on Analog Spiking Neural Network Chip. - Akiyo Nomura; Megumi Ito; Atsuya Okazaki; Masatoshi Ishii; SangBum Kim; Junka Okazawa; Kohji Hosokawa; Wilfried Haensch (ICONIP (7), 2018)

Performance Analysis of Spiking RBM with Measurement-Based Phase Change Memory Model. - Masatoshi Ishii; Megumi Ito; Wanki Kim; SangBum Kim; Akiyo Nomura; Atsuya Okazaki; Junka Okazawa; Kohji Hosokawa; Matthew BrightSky; Wilfried Haensch (ICONIP (5), 2019)

Training Large-Scale Spiking Neural Networks on Multi-core Neuromorphic System Using Backpropagation. - Megumi Ito; Malte J. Rasch; Masatoshi Ishii; Atsuya Okazaki; SangBum Kim; Junka Okazawa; Akiyo Nomura; Kohji Hosokawa; Wilfried Haensch (ICONIP (3), 2019)

Analysis of Effect of Weight Variation on SNN Chip with PCM-Refresh Method. - Akiyo Nomura; Megumi Ito; Atsuya Okazaki; Masatoshi Ishii; SangBum Kim; Junka Okazawa; Kohji Hosokawa; Wilfried Haensch (Neural Process. Lett., 2021)

Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers. - Atsuya Okazaki; Pritish Narayanan; Stefano Ambrogio; Kohji Hosokawa; Hsinyu Tsai; Akiyo Nomura; Takeo Yasuda; Charles Mackin; Alexander M. Friz; Masatoshi Ishii; Yasuteru Kohda; Katie Spoon; et al. (ISCAS, 2022)

Pattern Training, Inference, and Regeneration Demonstration Using On-Chip Trainable Neuromorphic Chips for Spiking Restricted Boltzmann Machine. - Uicheol Shin; Masatoshi Ishii; Atsuya Okazaki; Megumi Ito; Malte J. Rasch; Wanki Kim; Akiyo Nomura; Wonseok Choi 012; Dooyong Koh; Kohji Hosokawa; Matthew BrightSky; Seiji Munetoh; et al. (Adv. Intell. Syst., 2022)

Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited). - Hsinyu Tsai; Pritish Narayanan; Shubham Jain; Stefano Ambrogio; Kohji Hosokawa; Masatoshi Ishii; Charles Mackin; Ching-Tzu Chen; Atsuya Okazaki; Akiyo Nomura; Irem Boybat; Ramachandran Muralidhar; et al. (ISCAS, 2023)

Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited). - Geoffrey W. Burr; Pritish Narayanan; Stefano Ambrogio; Atsuya Okazaki; Hsinyu Tsai; Kohji Hosokawa; Charles Mackin; Akiyo Nomura; Takeo Yasuda; J. Demarest; Kevin Brew; Victor Chan; et al. (VLSI Technology and Circuits, 2023)

An analog-AI chip for energy-efficient speech recognition and transcription. - Stefano Ambrogio; Pritish Narayanan; Atsuya Okazaki; Andrea Fasoli; Charles Mackin; Kohji Hosokawa; Akiyo Nomura; Takeo Yasuda; An Chen 002; Alexander M. Friz; Masatoshi Ishii; Jose Luquin; et al. (Nat., 2023)

Analog-AI Hardware Accelerators for Low-Latency Transformer-Based Language Models (Invited). - Geoffrey W. Burr; H. Tsai; Irem Boybat; William Andrew Simon; Julian Büchel; Athanasios Vasilopoulos; Pritish Narayanan; Andrea Fasoli; Kohji Hosokawa; Manuel Le Gallo; M. Ishii; Yasuteru Kohda; et al. (CICC, 2025)

Analog AI Accelerators for Transformer-based Language Models: Hardware, Workload, and Power Performance. - H. Tsai; Hadjer Benmeziane; Irem Boybat; Julian Büchel; Pritish Narayanan; Manuel Le Gallo; S. Jain; Athanasios Vasilopoulos; W. Simon; Kohji Hosokawa; M. Ishii; Yasuteru Kohda; et al. (IMW, 2025)