Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration. - Izhar Zaidi; Atukem Nabina; Cedric Nishan Canagarajah; José L. Núñez-Yáñez (DSD, 2008)

Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based opensource processor. - Izhar Zaidi; Atukem Nabina; Cedric Nishan Canagarajah; José L. Núñez-Yáñez (FPL, 2008)

Energy optimization in a Network-on-Chip with dynamically reconfigurable processing nodes. - José L. Núñez-Yáñez; Mohammad Hosseinabady; Atukem Nabina; Izhar Zaidi (CCA/ISIC, 2009)

Dynamic Reconfiguration Optimisation with Streaming Data Decompression. - Atukem Nabina; José L. Núñez-Yáñez (FPL, 2010)

Exploring dynamically reconfigurable multicore designs with NoRC designer. - José L. Núñez-Yáñez; Arash Beldachi; Atukem Nabina; Mohammad Hosseinabady (HPCS, 2012)

Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform. - Atukem Nabina; José Luis Núñez-Yáñez (ACM Trans. Reconfigurable Technol. Syst., 2012)

Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding. - José Luis Núñez-Yáñez; Atukem Nabina; Eddie Hung; George Vafiadis (IEEE Trans. Very Large Scale Integr. Syst., 2012)