Aggressor aware repeater circuits for improving on-chip bus performance and robustness. - Atul Katoch; Sanjeev K. Jain; Maurice Meijer (ESSCIRC, 2003)

Adaptive threshold scheme to operate long on-chip buses at the limit of signal integrity. - Atul Katoch; Manish Garg; Evert Seevinck; Harry J. M. Veendrick (ESSCIRC, 2004)

Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems. - Daniele Rossi 001; A. Muccio; André K. Nieuwland; Atul Katoch; Cecilia Metra (IOLTS, 2004)

Reducing Cross-Talk Induced Power Consumption and Delay. - André K. Nieuwland; Atul Katoch; Maurice Meijer (PATMOS, 2004)

Isodelay output driver design using step-wise charging for low power. - Atul Katoch; Harry J. M. Veendrick (ESSCIRC, 2005)

Coding Techniques for Low Switching Noise in Fault Tolerant Busses. - André K. Nieuwland; Atul Katoch; Daniele Rossi 001; Cecilia Metra (IOLTS, 2005)

High speed current-mode signaling circuits for on-chip interconnects. - Atul Katoch; Harry J. M. Veendrick; Evert Seevinck (ISCAS (4), 2005)

Active Noise Cancellation Using Aggressor-Aware Clamping Circuit for Robust On-Chip Communication. - Atul Katoch; Maurice Meijer; Sanjeev K. Jain (VLSI Design, 2005)

Exploiting ECC Redundancy to Minimize Crosstalk Impact. - Daniele Rossi 001; André K. Nieuwland; Atul Katoch; Cecilia Metra (IEEE Des. Test Comput., 2005)

New ECC for Crosstalk Impact Minimization. - Daniele Rossi 001; André K. Nieuwland; Atul Katoch; Cecilia Metra (IEEE Des. Test Comput., 2005)

A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS. - Sergey Romanovsky; Atul Katoch; Arun Achyuthan; C. O'Connell; Sreedhar Natarajan; C. Huang; Chuan-Yu Wu; Min-Jer Wang; C. J. Wang; P. Chen; R. Hsieh (ISSCC, 2008)

12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications. - Michael Clinton; Hank Cheng; Hung-Jen Liao; Robin Lee; Ching-Wei Wu; Johnny Yang; Hau-Tai Hsieh; Frank Wu; Jung-Ping Yang; Atul Katoch; Arun Achyuthan; Donald Mikan; et al. (ISSCC, 2017)

A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications. - Jonathan Chang; Yen-Huei Chen; Gary Chan; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Sevic Chen; Peijiun Lin; Ching-Wei Wu; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; et al. (VLSI Technology and Circuits, 2023)