BIST for phase-locked loops in digital applications. - Stephen K. Sunter; Aubin Roy (ITC, 1999)

High Accuracy Stimulus Generation for A/D Converter BIST. - Aubin Roy; Stephen K. Sunter; Alessandra Fudoli; Davide Appello (ITC, 2002)

An Automated, Complete, Structural Test Solution for SERDES. - Stephen K. Sunter; Aubin Roy; Jean-Francois Cote (ITC, 2004)

On-Chip Digital Jitter Measurement, from Megahertz to Gigahertz. - Stephen K. Sunter; Aubin Roy (IEEE Des. Test Comput., 2004)

Structural tests for jitter tolerance in SerDes receivers. - Stephen K. Sunter; Aubin Roy (ITC, 2005)

Testing SerDes beyond 4 Gbps - changing priorities. - Stephen K. Sunter; Aubin Roy (CICC, 2007)

Purely Digital BIST for Any PLL or DLL. - Stephen K. Sunter; Aubin Roy (ETS, 2007)

A selt-testing BOST for high-frequency PLLs, DLLs, and SerDes. - Stephen K. Sunter; Aubin Roy (ITC, 2007)

Noise-Insensitive Digital BIST for any PLL or DLL. - Stephen K. Sunter; Aubin Roy (J. Electron. Test., 2008)

A Mixed-Signal Test Bus and Analog BIST with 'Unlimited' Time and Voltage Resolution. - Stephen K. Sunter; Aubin Roy (ETS, 2011)

Adaptive parametric BIST of high-speed parallel I/Os via standard boundary scan. - Stephen K. Sunter; Aubin Roy (ITC, 2011)

Contactless Test of IC Pads, Pins, and TSVs via Standard Boundary Scan. - Stephen K. Sunter; Aubin Roy (IEEE Des. Test Comput., 2012)